Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS

Abstract

We propose estimation techniques and compensation algorithms against CMOS device variability in an all-digital RF polar transmitter. The transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. The converters built with segmented banks consist of a large number of unit-weighted devices which exhibit a certain level of random and systematic mismatch. The techniques presented are employed in a commercial single-chip GSM/EDGE radio realized in 90 nm CMOS.