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In this paper, an LC-VCO design optimization methodology based on the g m /I D technique and on the exploration of all inversion regions of the MOS transistor is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semi-empirical models of MOS transistors and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design trade-offs are easily identified. Four LC-VCO designs in different inversion regions in a 90 nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4 GHz VCO operating in moderate inversion. The designed VCO draws 440 µA from a 1.2V power supply and presents a phase noise of −106.2 dBc/Hz at 400 kHz from the carrier.

In this paper, the MOS transistor (MOST) moderate-weak inversion region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low noise amplifiers (CS-LNA) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise figure-power consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the moderate-weak inversion region. Noise figure, power consumption and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their trade-offs. The Pareto-optimal design frontier obtained by calculation, -showing the moderate-weak inversion region as the optimum design zone-is re-verified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best FoM considering under-mW CS-LNAs published designs, consuming 684 µW, a noise figure of 4.36 dB, a power gain of 9.7 dB and an IIP3 of -4 dBm with load and source resistances of 50 Ω.

This paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitive to key specifications of the DUT. An optimized regression model based on ensemble learning is used to relate the digital signatures to the target specifications. The proposed test procedure is studied from an analytical point of view, and a demonstrator has been developed to prove the feasibility of the approach. This demonstrator features a 2.445GHz low-power LNA and a simple envelope detector, and has been

Abstract-This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Postlayout simulation results are provided to verify the functionality of the approach.

A simple on-chip procedure for testing embedded RF blocks is presented. It is based on the detection and spectral analysis of the two-tone response envelope of the Device Under Test (DUT). The main non-linearity specifications of the DUT can be easily estimated from the envelope signal without the need of expensive RF test equipment. Introduction: Nowadays, the advance in RF CMOS technologies has enabled the integration of complete transceivers in a single chip, which provides a significant reduction in manufacturing cost. However there is a simultaneous increase in the cost of testing and diagnosis of these devices. Their diverse specifications and high operating frequency, as well as the large impact of process variations in current deep sub-micron technologies, make necessary extensive tests, both complex and expensive to perform. Reducing RF test complexity and cost is still an open research topic that has been addressed in a number of different approaches. Recent work in this area includes defect modeling and failure diagnosis [1], alternate test [2], Design for Test (DfT) and Built-In-Self-Test (BIST) techniques [3]-[6], etc. In particular, BIST techniques have been identified as a solution to mitigate several RF test drawbacks [5]. In this context, the work in [6] proposes the use of a very simple envelope detector for RF test purposes. This reference

In recent years there has been a growing interest in electronic design automation methodologies for the optimizationbased design of radiofrequency circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle radiofrequency systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this work, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multi-objective optimization algorithms are used to design an entire radiofrequency system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.

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