In this paper, the MOS transistor (MOST) moderate-weak inversion region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low noise amplifiers (CS-LNA) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise figure-power consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the moderate-weak inversion region. Noise figure, power consumption and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their trade-offs. The Pareto-optimal design frontier obtained by calculation, -showing the moderate-weak inversion region as the optimum design zone-is re-verified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best FoM considering under-mW CS-LNAs published designs, consuming 684 µW, a noise figure of 4.36 dB, a power gain of 9.7 dB and an IIP3 of -4 dBm with load and source resistances of 50 Ω.