LC-VCO Design Optimization Methodology Based on the $g_m/I_D$ Ratio for Nanometer CMOS Technologies

Abstract

In this paper, an LC-VCO design optimization methodology based on the g m /I D technique and on the exploration of all inversion regions of the MOS transistor is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semi-empirical models of MOS transistors and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design trade-offs are easily identified. Four LC-VCO designs in different inversion regions in a 90 nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4 GHz VCO operating in moderate inversion. The designed VCO draws 440 µA from a 1.2V power supply and presents a phase noise of −106.2 dBc/Hz at 400 kHz from the carrier.

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

“…Our analyses will allow for the first time to gain insight into the theoretical details of this technique and its effective application, in addition to the oscillator performance optimization with respect to transconductance-to-current ratio (g m /I D ); for example, [22].…”

MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs

“…Modeling of MOST is done by using a semi-empirical model based on a lookup-table (LUT) [10], [22], [25] obtained by electrical DC and noise simulations, performed only once, on models qualified by the foundry of our Reference Technology. This way, it jointly considers second and higher order effects that appear in nanometer technologies, as discussed in [10].…”

“…Finding this Pareto frontier without using electrical optimization tools implies the implementation of an optimization method that considers the inversion region as its core variable. In this sense, this paper follows the same approach of [10]- [20], where optimization techniques for RF circuits applied before electrical simulation are proven as a suitable design strategy.…”

“…In this paper, the design method used follows the guidelines the authors enunciate in [10]; i.e. the application of semi-empirical modeling for RF devices (in particular MOST and inductors) and the use of analytical expressions of circuit's small-signal model in a developed ad-hoc design flow which arrange them together with the necessary decisions fixed by LNA specifications and technological constraints.…”

Design of low power CMOS LC VCO for direct conversion transceiver

“…Fiorelli et al [9] analyzed different inversion regions based on g m /I d for an LC VCO design using 90 nm CMOS technology. The differential LC VCO was designed in the moderate inversion region, consumed 440 mu A at a 1.2 V supply voltage, and produced 106.2 dBc/Hz phase noise at 400 kHz offset from the carrier.…”