Designers need accurate models to estimate 1/f noise in MOS transistors as a function of their size, bias point, and technology. Conventional models present limitations; they usually do not consistently represent the series-parallel associations of transistors and may not provide adequate results for all the operating regions, particularly moderate inversion. In this brief, we present a consistent, physics-based, one-equation-all-regions model for flicker noise developed with the aid of a one-equation-all-regions dc model of the MOS transistor.

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The design and test of a micropower signal conditioning circuit for a piezoresistive accelerometer is presented. The circuit is intended for sensing human body motion in rateadaptive cardiac pacemakers. A strategy is proposed to allow to handle the piezoresistive sensor with the desired level of consumption. Experimental results show the fabricated circuit is able to measure accelerations in the range from 0.04g to 0.34g with a total consumption of less than 3mA with supply voltages down to 2V.

Because of the extremely low amplitude of the input signal, the design of electro-neuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable electronics, because power consumption is restricted to few hundreds lW. In this work, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable medical devices, are demonstrated. The circuit design, and measurement results are presented, in both cases showing an excellent performance, and noise to power consumption trade-off. In the first circuit, a very simple low-pass G m -C chopper amplifier is used for flicker noise cancellation. It consumes only 28 mW, with a measured input referred noise and offset of 2 nV ffiffiffiffiffiffi Hz p , and 2.5 lV, respectively. In the second circuit, a ultra-low noise amplifier, a energyefficient DC-DC down-converter, and low voltage design techniques are combined, for the reduction of thermal noise with a minimum power consumption. Measured input referred noise in this case was 5.5 nV ffiffiffiffiffiffi Hz p at only 380 lW power consumption. Both circuits were fabricated in a 1.5 lm technology.

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This paper shows the development of a fully integrated G m -C 0.5-7 Hz bandpass amplifier (gain G = 400), for a piezoelectric accelerometer to be employed in rate adaptive pacemakers. The circuit, fabricated in a standard 0.8 micron CMOS technology, operates with a power supply as low as 2 V, consumes 230 nA of current, and has only a 2.1 µV rms input referred noise. Detailed circuit specifications, measurements, and a system performance comparative analysis are presented. The physical activity system includes a fully integrated G m -C rectifier and 3-second time average. Fully integrated very low frequency circuits were implemented with the aid of series-parallel current division in symmetrical OTAs. OTAs as low as 33 pS (equivalent to a 30 G resistor) were designed, fabricated, and tested.