Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel Current Mirrors

Arnaud, Alfredo; Fiorelli, Rafaella; Galup-Montoro, Carlos

doi:10.1109/jssc.2006.880606

Cited by 100 publications

(40 citation statements)

References 24 publications

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“…The impact of is first evaluated, which shows the of 's drain current can be expressed as (19) Assume the transistors follow the square-law drain-current model, the drain-current of due to the current factors are calculated as in (20), shown at the bottom of the page, where and are the current factors of the unit-NMOS and PMOS transistors, respectively. Thus, the percentage of of the total 's drain-current mismatch is given by (21), also shown at the bottom of the page.…”

Section: A Three-step Ncm Amplifier Under Transistor Mismatchesmentioning

confidence: 99%

See 1 more Smart Citation

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Zhang

Mak

Law

et al. 2015

IEEE J. Solid-State Circuits

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For better area and power efficiencies, rail-to-railoutput single-stage amplifiers are a potential replacement of their multi-stage counterparts, especially for display applications that entail massive buffer amplifiers in their column drivers. This paper describes a nested-current-mirror (NCM) technique for a single-stage amplifier to achieve substantial enhancements of DC gain, gain-bandwidth product (GBW) and slew rate (SR). Specifically, NCM is customizable for different mirror steps, and sub mirror ratios, to balance the performance metrics and capacitive-load ( ) drivability, avoiding any compensation passives while preserving a rail-to-rail output swing. Analytical treatments of the NCM technique in terms of performance limits and robustness reveal that the NCM amplifier can surpass the fundamental power-efficiency limit set by the basic differential-pair (DP) amplifier. Two prototypes, 3-step and 4-step NCM amplifiers, were fabricated in 0.18 m CMOS for systematic comparison with the DP amplifier. The former represents a robust design exhibiting 72 dB DC gain and 0.0028-0.27 MHz GBW over 0.15-15 nF with 80 phase margin (PM). The latter embodies an aggressive design attaining 84 dB DC gain and 0.013-1.24 MHz GBW over 0.15-15 nF with 62 PM. All amplifiers were sized for the same area (0.0013 mm ) and power (3.6 W).Index Terms-Area efficiency, CMOS, current mirror, DC gain, differential-pair (DP) amplifier, frequency compensation, gain-bandwidth product (GBW), low temperature polysilicon LCD, multi-stage amplifier, nested current mirror, rail-to-rail output swing, single-stage amplifier, slew rate (SR), stability.

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Section: A Three-step Ncm Amplifier Under Transistor Mismatchesmentioning

confidence: 99%

“…Similar derivation can be applied to the 4-step NCM to obtain . In addition to the (20) [20] to realize large ratio current mirrors with reduced current mismatch while multi-dimension current mirror layout techniques are employed in [21] for substantial current mismatch reduction.…”

Section: A Three-step Ncm Amplifier Under Transistor Mismatchesmentioning

confidence: 99%

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Zhang

Mak

Law

et al. 2015

IEEE J. Solid-State Circuits

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“…4, in order to achieve sub-1Hz low cut-off frequencies it is necessary to work with sub-nS OTA [11] as well as to use relatively large capacitors (200 − 300pF ).…”

Section: Capacitor Size Constraintsmentioning

confidence: 99%

Integrated programmable analog front-end architecture for physiological signal acquisition

Oreggioni¹,

Silveira²

2014

2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings

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A versatile front-end capable of acquiring a wide range of physiological signals, thus reusing the same design and hardware in different contexts, is a valuable goal both for biomedical research and medical devices. In this work we present such an "all-terrain" programmable integrated front-end architecture and the trade-offs associated to its design. A low noise preamplifier is implemented using a novel architecture based on a differential-difference amplifier which applies gm-C techniques for fixing the cut-off frequencies. Moreover, this architecture is extended to be applied to the other stages of the front-end. The main design trade-offs (noise-power, gain-power, noise-gain and linearity-gain) of the front-end architecture are discussed and their impacts in the design of the processing chain in terms of assignment of gain, noise, linearity and programmability to each stage are shown. The front-end is designed in a 0.5µm CMOS process. The gain is programmable between 57dB and 99dB, the high cut-off frequency is programmable between 116Hz and 5.2kHz, the low cut-off frequency is 18Hz, the maximum power consumption of the front-end is 11.2µA and its maximum equivalent input-referred noise voltage is 1.87µVrms.

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“…The transconductances values were selected following the guidelines in [22]: G m1 = 20 lS, G m2 = 683 nS, G m3 = 2.2 nS, C 1 = 78 pF and C 2 = 22 pF are poly1-poly2 capacitors. G m1,2,3 were implemented as a standard symmetrical OTAs using seriesparallel current division technique [23]. For G m1 the current copy factor from the differential pair to the output is 1:1, while for G m2 is 16:1, and for G m3 100:1.…”

Section: Gm-c Band-pass Filtermentioning

confidence: 99%

On the reduction of thermal and flicker noise in ENG signal recording amplifiers

Gak

Miguez

Bremermann

et al. 2008

Analog Integr Circ Sig Process

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Because of the extremely low amplitude of the input signal, the design of electro-neuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable electronics, because power consumption is restricted to few hundreds lW. In this work, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable medical devices, are demonstrated. The circuit design, and measurement results are presented, in both cases showing an excellent performance, and noise to power consumption trade-off. In the first circuit, a very simple low-pass G m -C chopper amplifier is used for flicker noise cancellation. It consumes only 28 mW, with a measured input referred noise and offset of 2 nV ffiffiffiffiffiffi Hz p , and 2.5 lV, respectively. In the second circuit, a ultra-low noise amplifier, a energyefficient DC-DC down-converter, and low voltage design techniques are combined, for the reduction of thermal noise with a minimum power consumption. Measured input referred noise in this case was 5.5 nV ffiffiffiffiffiffi Hz p at only 380 lW power consumption. Both circuits were fabricated in a 1.5 lm technology.

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Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel Current Mirrors

Cited by 100 publications

References 24 publications

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Integrated programmable analog front-end architecture for physiological signal acquisition

On the reduction of thermal and flicker noise in ENG signal recording amplifiers

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