-Several nanoscale computational fabrics based on various physical phenomena have been proposed in recent years. However, their integration with CMOS has only received limited attention. In this paper we explore some of these integration challenges focusing on registration and the overlay between layers. We propose and evaluate a new 3D integration approach by carefully mixing standard CMOS design rules and nanoscale constraints. We address the following questions: (i) How much overlay precision is necessary? (ii) What is the impact on yield if different overlays are used?, and (iii) How can we mitigate the overlay requirements? For a nanoprocessor design implemented in N 3 ASIC (a hybrid nanowire-CMOS fabric) we show that a 100% yield is achievable even for a today's known overlay of 3σ=±8nm (ITRS 2009). The N 3 ASIC fabric version retains 6X density advantage compared to a projected 16nm CMOS scaled design even after 3D integration.

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Emerging nano-device based architectures are expected to experience high defect rates associated with the manufacturing process. In this paper, we introduce a novel built-in heterogeneous fault-tolerance scheme, which incorporates redundant circuitry into the design to provide fault tolerance. A thorough analysis of the new scheme was carried out for various system level metrics. The implementation and analysis were carried out on WISP-0, a stream processor implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) fabric. We show that intelligent assignment of redundancy levels and nanoscalevoting strategies across WISP-0 greatly improves area, effective yield and performance for the nano-processor. The new scheme outperforms homogeneous schemes for a defect range of 3% to 9.75% where the metric used is the product of performance and effective yield.

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Current printability issues can be attributed to subwavelength lithography and its sensitivity to manufacturing process variations. Resulting process variations cause performance, yield and reliability problems. As noted in ITRS, conventional burn-in test is losing cost-effectiveness in reliability screening. In this paper, we use lithography process corner information in reliability screening. The lithographic process corner information is decoded from circuit measurements using a tester. We propose two methodologies for binning of dies based on Mean Time to Failure (MTTF). Lithography aware LUT based binning uses pre-estimated MTTF values to bin dies based on the detected litho-process corner. Lithography aware pattern based binning uses test patterns specific to litho-process corner along with existing techniques like burn-in test or Electrical Linewidth Metrology (ELM). Accurate determination of die level process corner is an important step employed in the proposed methodology. This work aims at: a) test Pattern generation for increased reliability test coverage incorporating manufacturing variations, b) utilization of die based process corner information for choosing the best test pattern set for improved fault coverage, c) achieving acceleration of infant mortality within the manufacturing test flow, and d) die-level determination of MTTF incorporating lithography process variation and hencedecreasing the binning-yield loss. Experiments on ISCAS'85 circuits for varying exposure dose and de-focus values show an average variation of 20-30nm in interconnect widths, resulting in a deviation of as much as 40% in the estimated MTTF. It is also observed that, for maximum fault coverage, the test vector set changes in size and pattern across various process corners.

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