The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depends on minute uncontrollable process variations, a low supply voltage can benefit PUFs by providing high sensitivity to variations and low power consumption as well. Motivated by this, we explore the feasibility of sub-threshold arbiter PUFs in 45nm CMOS technology. By modeling process variations and interconnect imbalance effects at the post-layout design level, we optimize the PUF supply voltage for the minimum power-delay product and investigate the trade-offs on PUF uniqueness and reliability. Moreover, we demonstrate that such a design optimization does not compromise the security of PUFs regarding modeling attacks and side-channel analysis attacks. Our final 64-stage subthreshold PUF design only needs 418 gates and consumes 0.047pJ energy per cycle, which is very promising for low-power wireless sensing and security applications.
Over the past few years, several novel nanoscale computing concepts have been proposed as potential post-complementary metal oxide semiconductor (CMOS) computing fabrics. In these, key focus is on inventing a faster and lower power alternative to conventional metal oxide semiconductor field effect transators. Instead, we propose a fundamental shift in mindset towards more functional building blocks, replacing simple switches with more sophisticated information encoding and computing based on alternate state variables to achieve a significantly more efficient and compact logic. Specifically, we propose wave computation enabled by magnetic spin wave interactions called as spin wave functions (SPWFs). In SPWFs, computation is based on wave interference and information can be encoded in a wave's phase, amplitude and frequency. In this paper, we provide an update on key fabric concepts and design aspects. Our analysis shows that circuit design choices can have a significant impact on overall fabric/device capabilities required and vice versa. Thereby, we adapt an integrated fabric-circuit exploration methodology. Control schemes for wave streaming and synchronization are also discussed with several SPWF circuit topologies. Our estimations show that significant area and power benefits can be expected for SPWF-based designs versus CMOS. In particular, for a 1-bit adder up to 40X area benefit and up to 304X power consumption reduction may be possible with SPWF-based implementation versus 45 nm CMOS.
-This paper argues for alternate state variables and new types of sophisticated devices that implement more functionality in one computational step than typical devices based on simple switches. Elementary excitations in solids enabling wave interactions are possible initial candidates to create such new devices. The paper focuses on magnon-based spin-wave-logic functions (SPWF) and presents high fan-in majority, weighted high fan-in majority, and frequency-multiplexed weighted high fan-in majority devices as initial SPWFs. Experiments proving feasibility are also shown. Benefits vs. scaled CMOS are quantified. Results show that for 128 or larger inputs even a 2.5µm SPWF carry-look-ahead adder implementation is faster than the 45nm CMOS version. The 45nm SPWF adder is expected to be significantly faster across the whole range of input widths. In particular, the 45nm SPWF CLA adder is estimated to be at least 77X faster than CMOS version for input widths equal to or greater than 1024. A second example of a counter circuit is presented to illustrate the considerable reduction in complexity possible vs. CMOS.
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