Design of Spin Wave Functions-Based Logic Circuits

Abstract

Over the past few years, several novel nanoscale computing concepts have been proposed as potential post-complementary metal oxide semiconductor (CMOS) computing fabrics. In these, key focus is on inventing a faster and lower power alternative to conventional metal oxide semiconductor field effect transators. Instead, we propose a fundamental shift in mindset towards more functional building blocks, replacing simple switches with more sophisticated information encoding and computing based on alternate state variables to achieve a significantly more efficient and compact logic. Specifically, we propose wave computation enabled by magnetic spin wave interactions called as spin wave functions (SPWFs). In SPWFs, computation is based on wave interference and information can be encoded in a wave's phase, amplitude and frequency. In this paper, we provide an update on key fabric concepts and design aspects. Our analysis shows that circuit design choices can have a significant impact on overall fabric/device capabilities required and vice versa. Thereby, we adapt an integrated fabric-circuit exploration methodology. Control schemes for wave streaming and synchronization are also discussed with several SPWF circuit topologies. Our estimations show that significant area and power benefits can be expected for SPWF-based designs versus CMOS. In particular, for a 1-bit adder up to 40X area benefit and up to 304X power consumption reduction may be possible with SPWF-based implementation versus 45 nm CMOS.

Majority Logic Synthesis for Spin Wave Technology

“…In SWDs, a compact realization of the majority gate is feasible. That is the logic primitive in this technology [3]. SWD technology if exploited correctly can result in more compact circuits than CMOS as the majority gate is more expressive than standard NAND/NOR gates.…”

System-level assessment and area evaluation of Spin Wave logic circuits

“…There is a lot of work done to physically and experimentally show the generation/excitation [13], [14], propagation [15], [16] and detection [17] of spin waves, nevertheless none of these publications focuses on the scaling challenges of the devices. Also there is a considerable body of work on the circuit design aspects of spin wave devices [3], [18].…”

“…A big part of these research efforts has been focused in producing devices that utilize the spin or magnetization of magnetically ordered materials as alternate state variable with respect to charge based-devices. A lot of work has be done in researching the capabilities of creating circuits that transfer information encoded in the phase of spin waves [2], [3]. However, it is not clear how these circuits will compare to modern CMOS nodes in terms of area and what the benefits of this technology would be if the circuits are scaled down.…”

Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS

“…The concept of SWD circuits was introduced in [2], but its modeling at nano-scaled dimensions was not studied with accuracy of micromagnetic simulations. In [10], the authors use SWDs to compose circuits but assume unrealistic capabilities of ME cells, without addressing their feasibility. Finally, [3] introduces a first order benchmarking of SWDs as circuits components but ignores any overhead sensing CMOS circuitry.…”