Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics

Vijayakumar, Priyamvada; Narayanan, Pritish; Koren, Israel; Krishna, C.M.; Moritz, Csaba Andras

doi:10.1109/nanoarch.2011.5941502

Cited by 8 publications

(3 citation statements)

References 24 publications

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“…Unconventional patterning approaches (e.g., nanoimprint lithography (NIL) [18]) can achieve very high density nanowire-arrays, but suffer from extremely poor overlay alignment. Therefore, in our manufacturing pathway, unconventional patterning approaches are used only in the beginning without any alignment or registration offset [5] [13]. All subsequent steps are lithographic and follow lithographic design rules [1].…”

Section: N 3 Asic Fabric Overviewmentioning

confidence: 99%

Experimental prototyping of beyond-CMOS nanowire computing fabrics

Rahman

Narayanan

Khasanvis

et al. 2013

2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

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Nanoscale 3D-integrated Application Specific ICs (N 3 ASICs) [1], a computing fabric based on semiconductor nanowire grids, is targeted as a scalable alternative to end-of-theline CMOS. In contrast to device-centric approaches like CMOS, N 3 ASIC design choices across device, circuit and architecture levels are geared towards reducing manufacturing requirements while focusing on overall benefits. In this fabric, regular arrays with limited customization imply mitigated overlay precision requirements, novel circuit styles with single-type cross-nanowire FETs eliminate the need for arbitrary fine-grain sizing, doping and routing. In addition, junctionless transistors eliminate the need for stringent control of doping profiles. In this paper, we present theoretical and experimental progress towards realizing a functional N 3 ASIC prototype with junctionless transistors as active cross-point devices. We first validate this device concept through detailed 3D device simulations. We then present a manufacturing pathway as well as show experimental results demonstrating a proof-of-concept metal-gated junctionless nanowire device and N 3 ASIC tile structure with sub-30nm nanowires.

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Section: N 3 Asic Fabric Overviewmentioning

confidence: 99%

Experimental prototyping of beyond-CMOS nanowire computing fabrics

Rahman

Narayanan

Khasanvis

et al. 2013

2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

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“…To study the impact of mask overlay a methodology was previously developed for a 2D-grid based NASIC fabric [32]. Overlay misalignment between successive masks were modeled as Gaussian random variables and Monte Carlo simulations were carried out in a custom simulator to determine the number of functioning chips.…”

Section: Introductionmentioning

confidence: 99%

N<sup>3</sup>ASICs: Designing nanofabrics with fine-grained CMOS integration

Panchapakeshan

Narayanan

Moritz

2011

2011 IEEE/ACM International Symposium on Nanoscale Architectures

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“…This sets a dramatic limit on the actual overall features that can be accomplished with reasonably precise alignment and good yield. Furthermore, recent work[Vijayakumar et al 2011] modeling overlay limited yields for NASICs has shown up to 75% yield for 3σ = ±5.7nm (manufacturing solutions known according to ITRS 2009) and 100% yield for 3σ = ±3.3nm (ITRS projection for 16nm CMOS.) 3 A note on Stochastic Interfacing: Stochastic interfacing is not required because NASICs do not assume reconfigurable devices where each device/crossbar needs to be programmed.…”

mentioning

confidence: 99%

Variability in Nanoscale Fabrics

Narayanan

Leuchtenburg

Kina

et al. 2013

J. Emerg. Technol. Comput. Syst.

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Emerging nanodevice-based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this article, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated approach enables to study in detail the impact of physical parameter variation across all fabric layers. A final contribution of the article includes novel techniques to address this impact. The variability framework, while generic, is explored extensively on the Nanoscale Application Specific Integrated Circuits (NASICs) nanowire fabric. For variation of σ = 10 in key physical parameters, the on current is found to vary by up to 3.5X. Circuit-level delay shows up to 118% deviation from nominal. Monte Carlo simulations using an architectural simulator found 67% nanoprocessor chips to operate below nominal frequencies due to variation. New built-in variation mitigation and fault-tolerance schemes, leveraging redundancy, asymmetric delay paths and biased voting schemes, were developed and evaluated to mitigate these effects. They are shown to improve performance by up to 7.5X on a nanoscale processor design with variation, and improve performance in designs relying on redundancy for defect tolerance, without variation assumed. Techniques show up to 3.8X improvement in effective-yield performance products even at a high 12% defect rate. The suite of techniques provides a design space across key system-level metrics such as performance, yield and area. . 2013. Variability in nanoscale fabrics: Bottom-up integrated analysis and mitigation.

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Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics

Cited by 8 publications

References 24 publications

Experimental prototyping of beyond-CMOS nanowire computing fabrics

Experimental prototyping of beyond-CMOS nanowire computing fabrics

N<sup>3</sup>ASICs: Designing nanofabrics with fine-grained CMOS integration

Variability in Nanoscale Fabrics

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