N³ASICs: Designing nanofabrics with fine-grained CMOS integration

Experimental prototyping of beyond-CMOS nanowire computing fabrics

“…Benchmarking results of N 3 ASIC logic (a processor design, WISP-0 [1]) showed 3x density and 5x active power benefits against equivalent CMOS design at 16nm [1], and the 10T-NWRAM showed 2x performance and 35x leakage improvement with comparable area and active power, when compared with 16nm CMOS SRAM [3] [4]. These benefits are attained at a significantly relaxed overlay.…”

“…N 3 ASIC relaxes manufacturing requirements through simplified regular grid-based layouts without arbitrary placement and routing, and uses single-type, uniformly sized transistors. Benchmarking results at 16nm for a processor design show N 3 ASICs to be up to 3x denser and 5x more power efficient than an equivalent CMOS design [1]. Benchmarking results for N 3 ASIC volatile memory shows 2x performance and 35x leakage power benefits, when compared to CMOS SRAM at 16nm [3] [4].…”

“…According to ITRS the overlay precision requirements for 16nm CMOS would be ±3nm [2], a precision for which manufacturing solutions are as yet unknown. To mitigate manufacturing challenges and to maintain technology scaling benefits at nanoscale, while maximizing system level benefits, we proposed a novel computing fabric called Nanoscale 3D Application Specific Integrated Circuits (N 3 ASIC) [1]. N 3 ASIC relaxes manufacturing requirements through simplified regular grid-based layouts without arbitrary placement and routing, and uses single-type, uniformly sized transistors.…”

“…The paper is organized as follows: In section II, we present an overview of the fabric and show its core components including the junctionless device; in section III, we present the detailed manufacturing pathway; in section IV, we highlight _______________________________ *Mostafizur Rahman 1 and Pritish Narayanan 2 contributed equally.…”

Parameter variation sensing and estimation in nanoscale fabrics

“…The proposed sensor designs for both systematic and random variations are also directly applicable to the Nanoscale 3-D Application Specific Integrated Circuits (N 3 ASIC) [23], [24], and the variability sensing methodology can be extended to other regular nanoscale computing fabrics in general. Several extensions exist to NASICs and there are other circuit styles also proposed but the approach for variability estimation applies across all of them.…”