Experimental prototyping of beyond-CMOS nanowire computing fabrics

Abstract

Nanoscale 3D-integrated Application Specific ICs (N 3 ASICs) [1], a computing fabric based on semiconductor nanowire grids, is targeted as a scalable alternative to end-of-theline CMOS. In contrast to device-centric approaches like CMOS, N 3 ASIC design choices across device, circuit and architecture levels are geared towards reducing manufacturing requirements while focusing on overall benefits. In this fabric, regular arrays with limited customization imply mitigated overlay precision requirements, novel circuit styles with single-type cross-nanowire FETs eliminate the need for arbitrary fine-grain sizing, doping and routing. In addition, junctionless transistors eliminate the need for stringent control of doping profiles. In this paper, we present theoretical and experimental progress towards realizing a functional N 3 ASIC prototype with junctionless transistors as active cross-point devices. We first validate this device concept through detailed 3D device simulations. We then present a manufacturing pathway as well as show experimental results demonstrating a proof-of-concept metal-gated junctionless nanowire device and N 3 ASIC tile structure with sub-30nm nanowires.

Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

“…The functionality of these components and structures depends on their material types and geometries. This manufacturing pathway is similar with another non CMOS based 3D IC fabric we proposed earlier, called Skybridge [6]- [9] and with a device that we experimentally demonstrated at a sub 30-nm scale [10]. The detailed manufacturing pathway is covered in Section IV.…”

“…The device behavior is modulated by the work function difference between gate electrodes and the channels. The concept of this type of transistors has been well researched [11], and also experimentally demonstrated in our group [10]. Although Junctionless device is often considered as providing lower on-current and somewhat worse device-level performance, in S3DC it is a part of a true fine-grained 3D integration solution, with dense connections and design, that overall yields higher performance at the fabric-level despite a somewhat sub-optimal device vs state-of-the-art FinFETs.…”

SkyNet: Memristor-based 3D IC for artificial neural networks

“…Figure 6 and Figure Because of their structural simplicity, these transistors can be stacked on the vertical nanowires to form 3D neuron circuits thus achieving very high density. These types of transistors have been well researched [17] and experimentally demonstrated by our group [18]. …”

Manufacturing pathway and experimental demonstration for nanoscale fine-grained 3-D integrated circuit fabric

“…1A. The manufacturing pathway is derived based on process, device simulations and our experimental demonstration of Junctionless transistor in 2-D [4], and uses existing foundry processes. The process flow starts with substrate doping (Fig.…”