Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

Li, Mingyu; Shi, Jiajun; Rahman, Mostafizur; Khasanvis, Santosh; Bhat, Sachin; Moritz, Csaba Andras

doi:10.1109/isvlsi.2016.56

“…Skybridge-3D-CMOS (S3DC) is a vertically composed fine-grained 3D CMOS IC technology [11] [12] [13] [14].…”

Section: Skybridge-3d-cmos Fabric Overviewmentioning

confidence: 99%

“…Confronted with the limitations in routability and PPA benefits, we proposed Skybridge-3D-CMOS (S3DC), a vertically-composed fine-grained 3D CMOS technology, which features much improved pin access, routing flexibility, and is based on fine-grained vertical circuits yielding dramatic efficiencies [11] [12] [13] [14] [15]. Results have shown that S3DC leads to significant benefits in power, performance and density, with 9.7 to 71X PPA benefits vs. the state-of-art transistor-level monolithic 3D approach, while maintaining excellent routability.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Based Thermal Evaluation for Vertically-Composed Fine-Grained 3D CMOS

Li¹,

Kulkarni²,

Bhat³

et al. 2022

Preprint

0

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<p>Thermal management in 3D integrated circuits is a critical challenge due to their high computational density. Heat dissipation paths from top circuit layers through bottom layers to substrate are heavily constraining heat extraction. Various thermal management frameworks have been proposed to address thermal issues in different granularities. All these frameworks require a thermal evaluation stage that characterizes the thermal profile of large designs with fast runtime. In this work, we present a machine learning based thermal evaluation method that predicts all standard cell temperatures based on features extracted from circuit CAD files. We have built thermal resistance networks for 10 benchmark circuits. We performed simulations to achieve the thermal data, and trained the thermal model with the data. The model is highly accurate and can identify all over-heated cells that need to be thermally-optimized. Runtime overhead is minimal. For a 435k-cell SPARC T2 core, the runtime for predicting all cell temperatures is as small as 3.12s, which is negligible compared to the runtime of other physical design stages. </p>

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“…Skybridge-3D-CMOS (S3DC) is a vertically composed fine-grained 3D CMOS IC technology [11] [12] [13] [14].…”

Section: Skybridge-3d-cmos Fabric Overviewmentioning

confidence: 99%

“…Confronted with the limitations in routability and PPA benefits, we proposed Skybridge-3D-CMOS (S3DC), a vertically-composed fine-grained 3D CMOS technology, which features much improved pin access, routing flexibility, and is based on fine-grained vertical circuits yielding dramatic efficiencies [11] [12] [13] [14] [15]. Results have shown that S3DC leads to significant benefits in power, performance and density, with 9.7 to 71X PPA benefits vs. the state-of-art transistor-level monolithic 3D approach, while maintaining excellent routability.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Based Thermal Evaluation for Vertically-Composed Fine-Grained 3D CMOS

Li¹,

Kulkarni²,

Bhat³

et al. 2022

Preprint

0

View full text Add to dashboard Cite

<p>Thermal management in 3D integrated circuits is a critical challenge due to their high computational density. Heat dissipation paths from top circuit layers through bottom layers to substrate are heavily constraining heat extraction. Various thermal management frameworks have been proposed to address thermal issues in different granularities. All these frameworks require a thermal evaluation stage that characterizes the thermal profile of large designs with fast runtime. In this work, we present a machine learning based thermal evaluation method that predicts all standard cell temperatures based on features extracted from circuit CAD files. We have built thermal resistance networks for 10 benchmark circuits. We performed simulations to achieve the thermal data, and trained the thermal model with the data. The model is highly accurate and can identify all over-heated cells that need to be thermally-optimized. Runtime overhead is minimal. For a 435k-cell SPARC T2 core, the runtime for predicting all cell temperatures is as small as 3.12s, which is negligible compared to the runtime of other physical design stages. </p>

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“…Skybridge offers a family of circuit-styles to be implemented such as NP-Dynamic Skybridge (NP-D-SB) [12] and Skybridge-3D-CMOS (S3DC) [13]. In this work, we focus on S3DC because it uses a static circuit style and fits well into the commercial CAD tools based ASIC design flow.…”

Section: Overview Of Skybridgementioning

confidence: 99%

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

Shi

¹

,

Li

²

,

Moritz

³

2017

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

Self Cite

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Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC technologies using Through Silicon Via or Monolithic Inter-layer Via alleviate some of these challenges, they follow a similar layout and routing mindset as 2D CMOS. This is insufficient to address routing requirements in high-density 3D ICs and even causes severe routing congestion at large-scale designs, limiting their benefits and scalability. Skybridge is a recently proposed fine-grained 3D IC fabric relying on vertical nanowires that presents a paradigm shift for scaling, while addressing associated 3D connectivity and manufacturability challenges. Skybridge's core fabric components enable a new 3D IC design approach with vertically-composed logic gates, and provide a greater degree of routing flexibility compared to conventional 2D and 3D ICs leading to much larger benefits and future scalability. In this paper, we present a methodology using relevant metrics to evaluate and quantify the benefits of Skybridge vs. state-of-the-art transistor-level monolithic 3D IC (T-MI) and 2Din terms of routability and its impact on large-scale circuits. This is enabled by a new device-to-system design flow with commercial CAD tools that we developed for large-scale Skybridge IC designs in 16nm node. Evaluation for standard benchmark circuits shows that Skybridge yields up to 1.6x lower routing demand against T-MI with no routing congestion (routing demand to resource ratio < 1) at all metal layers. This 3D routability in conjunction with compact vertical gate design in Skybridge translate into benefits of up to 3x lower power and 11x higher density over 2D CMOS, while TLM-3DIC approach only has up to 22% power saving and 2x density improvement over 2D CMOS.

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Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

Cited by 8 publications

References 18 publications

Machine Learning Based Thermal Evaluation for Vertically-Composed Fine-Grained 3D CMOS

Machine Learning Based Thermal Evaluation for Vertically-Composed Fine-Grained 3D CMOS

Machine Learning Based Thermal Evaluation for Vertically-Composed Fine-Grained 3D CMOS

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

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