This paper presents the first parameterized, SPICEcompatible compact model of a Graphene Nano-Ribbon FieldEffect Transistor (GNRFET) with doped reservoirs, also known as MOS-type GNRFET. The current and charge models closely match numerical TCAD simulations. In addition, process variation in transistor dimension, line edge roughness, and doping level in the reservoirs are accurately modeled. Our model provides a means to analyze delay and power of graphene-based circuits under process variation, and offers design and fabrication insights for graphene circuits in the future. We show that line edge roughness severely degrades the advantages of GNRFET circuits; however, GNRFET is still a good candidate for lowpower applications.

This paper presents an accurate analytical compact model for Schottky-barrier-type graphene nanoribbon field-effect transistors (SB-GNRFETs). This is a physics-based analytical model for the current-voltage (I-V ) characteristics of SB-GNRFETs. The proposed model considers various design parameters and process variation effects, including graphenespecific line-edge roughness, which allows thorough exploration and evaluation of SB-GNRFET circuits. We develop accurate approximations of SB tunneling, channel charge, and current, which provide accurate results while maintaining model compactness. We evaluate the effect of design parameters and process variations on the performance of SB-GNRFETs. We also compare circuit-level performance of SB-GNRFETs with multigate (MG) Si-CMOS (e.g., FinFETs). Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS, although GNR-specific process variation, especially the line-edge roughness, would significantly downgrade such an advantage; the EDP of the ideal SB-GNRFET (assuming no process variation) is ∼2.5% of that of Si-CMOS, while the EDP of the nonideal case with process variation is ∼68% of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (nonideal) SB-GNRFET is ∼0.88% (54%) EDP of that of Si-CMOS as the technology nodes scale down to 7 nm.Index Terms-Graphene nanoribbon field-effect transistor (GNRFET), nanoelectronics, Schottky barrier (SB), SPICE model.

Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

No abstract