Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Izadinasab

2021

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Graphene nanoribbon and transition metal dichalcogenide field-effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal-oxide-semiconductor (MOS) transistor in future technologies. Their competence must be proven through the study and evaluation of various circuits, including static random access memories (SRAMs). Therefore, this paper presents a single-ended 12T (SE12T) SRAM cell designed using GNRFETs and TMDFETs to evaluate their performance. The proposed SE12T cell designed with GNRFETs/TMDFET device improves read static noise margin by 1.95Â/3.20Â and incurs a penalty of 1.16Â/1.14Â in read delay compared to the GNRFETs/TMDFET-based fully differential 8T cell through a read buffer, decoupling the bitline from the storing nodes during the read operation. Furthermore, two transmission gates (TGs) placed inside the cell core cut off the feedback of cross-coupled inverters pair during the write operation, enhancing write static noise margin by 1.65Â/1.71Â. These two TGs along with high logic level of virtual ground (V GND ) control signal during hold mode reduce leakage power. Existence of a higher number of p-type MOS (PMOS) devices, the presence of stacked transistors, and being single-ended bitcell further reduce this metric, nearly 1.48Â/1.17Â designed with GNRFETs/TMDFET device as compared to FD8T. Furthermore, it is observed from the results that GNRFET-based designs have better performance than those of their TMDFET counterparts. The proposed cell eliminates write half-select disturb, and therefore, bit-interleaving architecture can be applied to reduce multi-bit errors.

Section: Read Stabilitymentioning

confidence: 99%

Section: Simulation Setupmentioning

confidence: 99%

Section: Read Stabilitymentioning

confidence: 99%

Section: Write-abilitymentioning

confidence: 99%

Section: Read Delaymentioning

confidence: 99%

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Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

Izadinasab

2021

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A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications

2022

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The design of power‐efficient SRAM cells is necessary for biomedical applications such as body area networks (BANs) to extent their battery life. SRAM cell's power consists of two main components, including leakage power and dynamic power, in which the former overcomes the latter in advanced technology. This paper presents a low‐leakage single‐bitline 9T (L2SB9T) SRAM cell. The proposed design is free from read‐disturbance issue and eliminates writing “1” problem. The results are carried out by utilizing HSPICE and 16‐nm CMOS PTM at a 0.7 V, 25°C, and under severe PVT variations. The proposed L2SB9T SRAM cell is comprehensively compared with other recently published SRAM cells including conventional 6T, write/read enhanced 8T (WRE8T), transmission‐gate 9T (TG9T), read‐disturb‐free 9T (RDF9T), fully differential 10T (Chang10T), data‐independent read port 10T (DIRP10T), and single‐bitline 11T (SB11T). It shows at least 1.26X/1.07X/1.01X improvement in read static noise margin (RSNM)/write static noise margin (WSNM)/write margin (WM). Furthermore, the leakage power is reduced by the proposed cell, at least 1.137X. Moreover, the suggested cell consumes the third/second best dynamic read/write power, which is 1.42X/1.37X lower than that of conventional 6T SRAM cell. The proposed L2SB9T SRAM cell performs its read/write operation reliably by showing at least 1.71X narrower speared in RSNM compared to the best SRAM cell and third best WM variability. For all these improvements, the proposed L2SB9T SRAM cell incurs a 4.20X/1.06X/1.808X penalty in read delay/write delay/layout area when compared with the best SRAM cells, that is, the Chang10T/6T/6T.

Improved read/write assist mechanism for 10‐transistor static random access memory cell

2022

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This paper presents a robust low‐power 10T SRAM cell (RLP10T) with a novel read/write assist mechanism, improving both read static noise margin (RSNM) and write static noise margin (WSNM) simultaneously. To assess its relative strength, we compared the proposed cell with recently published SRAM cells such as WRE8T, 10T‐P1, HFBS10T, WALP11T, and SE11T in 16‐nm CMOS technology node. The RLP10T cell shows 3.55/1.07 times higher/lower RSNM compared to the WRE8T/WALP11T cell and offers at least 1.10 times higher WSNM. Due to the presence of three series‐connected transistors in its read path, which includes a strong pull‐down transistor, the proposed design shows 1.23 times shorter read delay (TRA) than that of 10T‐P1/HFBS10T cell. The proposed cell incurs a penalty of high write delay (TWA) due to its long write path. However, it exhibits the fourth (second)‐best read (write) power, attributed to its single‐ended structure and lower read (write) frequency. It also dissipates acceptable leakage power due to its single‐bitline structure and the presence of stacked transistors in its read path and pull‐down path of one of the inverters in the cell core. Subjected to the severe process, voltage, and temperature variations, the RLP10T cell offers at least 1.31/1.09/1.03 times lower variability in RSNM/WSNM/TRA at VDD = 0.7 V, at the cost of 1.22 times area overhead compared to the WRE8T cell.