3-D integration requirements for hybrid nanoscale-CMOS fabrics

Abstract

-Several nanoscale computational fabrics based on various physical phenomena have been proposed in recent years. However, their integration with CMOS has only received limited attention. In this paper we explore some of these integration challenges focusing on registration and the overlay between layers. We propose and evaluate a new 3D integration approach by carefully mixing standard CMOS design rules and nanoscale constraints. We address the following questions: (i) How much overlay precision is necessary? (ii) What is the impact on yield if different overlays are used?, and (iii) How can we mitigate the overlay requirements? For a nanoprocessor design implemented in N 3 ASIC (a hybrid nanowire-CMOS fabric) we show that a 100% yield is achievable even for a today's known overlay of 3σ=±8nm (ITRS 2009). The N 3 ASIC fabric version retains 6X density advantage compared to a projected 16nm CMOS scaled design even after 3D integration.

Experimental prototyping of beyond-CMOS nanowire computing fabrics

“…These benefits are attained at a significantly relaxed overlay. Our simulation results showed 100% yield can be achieved in N 3 ASIC manufacturing for an overlay of ±8nm [5]; this is considerably less stringent than CMOS, which requires an overlay precision of ±3nm at 16nm.…”

“…In addition, due to N 3 ASICs regular physical layout and choices at all levels of abstraction, the overlay alignment requirements are significantly less than in CMOS. Our yield simulation results show 100% yield can be achieved with relaxed overlay of ±8nm for N 3 ASIC fabric implementation at 16nm technology node [5]. The process technology for such precision is known today and is in use.…”

“…Unconventional patterning approaches (e.g., nanoimprint lithography (NIL) [18]) can achieve very high density nanowire-arrays, but suffer from extremely poor overlay alignment. Therefore, in our manufacturing pathway, unconventional patterning approaches are used only in the beginning without any alignment or registration offset [5] [13]. All subsequent steps are lithographic and follow lithographic design rules [1].…”

Nanowire field-programmable computing platform

“…The a-priori assembly/directpatterning of NW layer before any conventional lithographic step (e.g., for contacts/vias) means that (i) registration requirement is effectively minimized, allowing potentially cost-effective nanomanufacturing techniques to be used; (ii) overlay alignment requirements exist only between subsequent lithographic masks. Our prior work [6] shows this can be 3σ = 8nm for 16nm node and manufacturing techniques to achieve this are already optimized [2]. Junctionless channel transistors further simplify manufacturing and uniform connectivity at NW tile I/Os implies standard litho-design rules can apply between layers using standard vias [6].…”

“…Our prior work [6] shows this can be 3σ = 8nm for 16nm node and manufacturing techniques to achieve this are already optimized [2]. Junctionless channel transistors further simplify manufacturing and uniform connectivity at NW tile I/Os implies standard litho-design rules can apply between layers using standard vias [6].…”