Towards efficient on-chip sensor interconnect architecture for multi-core processors

Phanibhushana, Bharath; Vijayakumar, Priyamvada; Shabadi, Prasad; Prabhu, Gayatri; Kundu, Sandip

doi:10.1109/socdc.2010.5682909

Cited by 7 publications

(1 citation statement)

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“…No discussion of the hardware needed to perform data analysis or system control is presented. Phanibhushana et al [9] limit their study to a tree-like interconnect for sensor data collection. Although lightweight, this type of interconnect does not allow for the broadcast of time-critical sensor data.…”

Section: A Previous Multi-core Sensing Systemsmentioning

confidence: 99%

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

Zhao

Burleson

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Contemporary multi-core architectures deployed in embedded systems are expected to function near the operational limits of temperature, voltage, and device wear-out. To date, most on-chip sensing systems have been designed to collect and use sensor information for these parameters locally. In this paper, a new sensing system to enhance multi-core dependability which supports both the local and global distribution of sensing data in embedded processors is considered. The benefit of the new sensing architecture is verified using the broadcast of microarchitectural parameter signatures which can be used to identify impending voltage droops. Low-latency broadcasts are supported for a range of sensor data transfer rates. Up to a 9% performance improvement for a 16-core system is determined via the use of the distributed voltage droop sensor information (5.4% on average). The entire sensing system, including broadcasting resources, requires about 2.6% of multi-core area.

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Section: A Previous Multi-core Sensing Systemsmentioning

confidence: 99%