Three-dimensional (3D) integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3D-integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting "decap" die and through-vias, are discussed in this paper.

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Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such technologies are not suitable for highperformance chips due to ineffective power delivery and heat removal. This is important because high performance chips are projected to dissipate more than 100W/cm 2 and require more than 100A of supply current. Consequently, when such chips are stacked, the challenges in power delivery and cooling become greatly exacerbated. Thus, revolutionary interconnection and packaging technologies will be needed to address these limits [1]. This paper reports, for the first time, the configuration, fabrication, and experimental results of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for high-performance chips. The key behind this 3D platform is the ability to process integrate, at the wafer-level, electrical and microfluidic interconnection networks on the wafer containing the electrical circuitry and assemble such chips using conventional flip-chip technology.

Strain measurements are demonstrated for through-silicon vias (TSVs) using synchrotron x-ray diffraction to characterize the effect of copper via dimensions and liner materials. Reduction in strains in the silicon around TSVs is observed for the TSVs with smaller via diameters and the TSVs with a thicker polymer liner. To interpret the measured two-dimensional (2D) TSV strain distribution maps of the three-dimensional (3D) TSV strains, a data averaging method based on the energy dependent x-ray absorption is implemented along with additional considerations from the sample preparation by means of an indirect comparison methodology. V

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Interlayer grating-to-grating optical interconnect coupling efficiency is simulated and optimized using rigorous coupled-wave analysis (RCWA) for the case of binary rectangular-groove gratings. The "equivalent index slab (EIS)" concept is proposed to alleviate the numerical sensitivity problem inherent in the RCWA-leaky-wave approach, making the method applicable to any multilayer structure that has an arbitrary grating profile, large refractive-index differences, and a limited grating length. The method is easy to implement and computationally efficient and can provide optimal designs based on the system designer's need. To determine the viability of the RCWA-EIS approach, results are compared to those obtained using the finite-difference time-domain method, and an excellent agreement is found.