Strain measurements are demonstrated for through-silicon vias (TSVs) using synchrotron x-ray diffraction to characterize the effect of copper via dimensions and liner materials. Reduction in strains in the silicon around TSVs is observed for the TSVs with smaller via diameters and the TSVs with a thicker polymer liner. To interpret the measured two-dimensional (2D) TSV strain distribution maps of the three-dimensional (3D) TSV strains, a data averaging method based on the energy dependent x-ray absorption is implemented along with additional considerations from the sample preparation by means of an indirect comparison methodology. V

To study thermomechanical strain induced by the mismatch of coefficients of thermal expansion in through-silicon vias (TSVs) and thus provide fundamental understanding of TSV reliability, strain measurements have been performed with synchrotron x-ray diffraction (XRD). The measured strains are available as two-dimensional (2D) distribution maps, whereas the strain distributions in TSVs are three-dimensional (3D) in nature. To understand this 3D to 2D data projection process, a data interpretation method based on beam intensity averaging is proposed and validated with measurements. The proposed method is applicable to XRD strain measurements on thin as well as thick samples.

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Modern high-performance computing systems and data centers are implemented as many-core server systems. Current state of the art data centers have server racks with pluggable boards where each board has many multi-core processors and memory units. These boards are connected via electrical or optical cables. In such systems, communication bandwidth between the high-speed microprocessor cores and the memory is limited. To leverage full performance of these powerful chips, it is required to provide high memory bandwidth as well as effective power delivery and heat removal solutions. To address these challenges in high performance computing systems, we present a 3D packaging solution that includes a novel silicon interposer with electrical, optical, and fluidic (trimodal) interconnects and through-silicon vias (TSVs). The electrical TSVs in the silicon interposer enable power and signal delivery from motherboard to chips stacked on top of the interposer. The optical TSVs in the silicon interposer can provide ultra-high bandwidth communication between chips on different silicon interposers through motherboard level optical links. The fluidic TSVs enable a coolant to be routed from the motherboard to the chips on the silicon interposer. We have fabricated and characterized polymer-clad electrical TSVs (for low stress) with diameter that meets ITRS projections for high-performance computing systems. Using the same polymer used for the cladding of electrical TSVs, we have fabricated and characterized optical TSVs adjacent to electrical TSVs. Spin coating of the photodefinable polymer for electrical and optical TSVs is done in single step. Fabrication of fluidic TSVs can be done using the same cladding as that of the polymer-clad electrical TSVs without electroplating the copper. This leaves behind an empty polymer-clad via which can be used as a fluidic TSV. I: IntroductionThe performance of a processor is commonly measured as the number of instructions it processes per unit time. For high performance and utilization of the processor, the rate at which memory supplies instructions and data to the processor must match with the rate at which the processor is processing them. With the migration towards multi-core and multi-threading, the memory gap problem becomes more acute since now multiple processors on a single chip will increase the memory bandwidth demand. Thus, all the performance benefits of this processor cannot be fully leveraged because memory speeds are much slower compared to the processor speed [1, 2]. Fig. 1 shows scaling in processor frequencies and the memory speed over the past years. To solve this problem, we must improve the memory throughput and reduce the memory latency which includes interconnect delay in addition to memory access delay. This was quantified with analytical simulations to determine the effect of increased memory bandwidth on a processor chip, and we see that performance increase is proportional to the available memory bandwidth. Fig. 2 shows that throughput increases from 96 BIPS (bi...

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