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Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such technologies are not suitable for highperformance chips due to ineffective power delivery and heat removal. This is important because high performance chips are projected to dissipate more than 100W/cm 2 and require more than 100A of supply current. Consequently, when such chips are stacked, the challenges in power delivery and cooling become greatly exacerbated. Thus, revolutionary interconnection and packaging technologies will be needed to address these limits [1]. This paper reports, for the first time, the configuration, fabrication, and experimental results of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for high-performance chips. The key behind this 3D platform is the ability to process integrate, at the wafer-level, electrical and microfluidic interconnection networks on the wafer containing the electrical circuitry and assemble such chips using conventional flip-chip technology.

This paper describes an improved method of forming and removing seed layers for through-silicon-vias (TSVs) in applications such as MEMS, sensors and packaging (silicon carrier, for example). A 'mesh seed layer' is proposed to reduce the pinch-off time and facilitate simpler and mechanical-free removal, the latter being possibly important when sensitive MEMS/sensor devices are pre-fabricated on the wafer. As a result, the proposed process may serve as a post-MEMS/sensor method of forming TSVs.

Through-silicon via (TSV) technology, an enabler for 3D ICs, has evolved, enabling thinner and shorter TSVs within substantially thinned wafers to achieve faster interconnects, large bandwidth density, and low power consumption. Yet, heat dissipation in 3D ICs becomes more and more challenging, especially in applications that require stacking of multiple processor and memory chips. Microfluidic cooling has been proposed as a solution to reject heat from 3D stacks that contain processor chips. However, current liquid cooling technology inevitably increases the wafer thickness, which is contrary to TSV technology trend. To date, little work has been done to optimize heat sink design to benefit TSV performance, and no attempt has been made to analyze the corresponding impact of a particular heat sink design on the performance of the electrical TSVs. A heat sink design without consideration of TSV performance can greatly diminish the advantages of 3D ICs. This paper presents a holistic cooling solution for 3D ICs, which not only meets thermal requirements, but also minimizes TSV parasitics that impact latency, bandwidth density, and power consumption. This paper will report: a) the design of a 3D-centric heat sink, b) the fabrication of the heat sink and associated high aspect ratio integrated TSVs, c) the thermal testing of the liquid-cooled heat sink and comparison to air-cooled heat sink, and d) the impact of the heat sink geometry on TSV capacitance.

Heat removal technologies are among the most critical needs for 3D integration of high-performance microprocessors. As high performance chips are projected to dissipate more than 100W/cm 2 and require more than 100A of supply current, integrating high performance chips in a 3D stack greatly exacerbates challenges in power delivery and cooling of chips within the stack.This paper reports the configuration of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for 3D architectures with integrated high-performance processors in the 3D stack. The researchers demonstrate the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. The on-chip integrated microchannel heat sinks enable cooling of >100W/cm 2 of each high power density chip. A key element in this platform is the ability to assemble chips with electrical and fluidic I/Os and seal fluidic interconnections at each strata interface. Three assembly and fluidic sealing techniques are discussed. Fabrication, assembly, and experimental results of the novel fluidic sealing technologies that enable the microfluidic network in the inter-layer liquid cooling 3D integration platform are also reported.

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