A ‘mesh’ seed layer for improved through-silicon-via fabrication

Lai, James S.; Yang, Hyung Suk; Chen, Hang; King, C.; Zaveri, Jesal; Ravindran, Ravishankar; Bakir, Muhannad S.

doi:10.1088/0960-1317/20/2/025016

Cited by 19 publications

(12 citation statements)

References 13 publications

(15 reference statements)

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“…TSVs were fabricated with silicon dioxide and photodefined polymer (SU-8) liners. With respect to the fabrication of TSVs with silicon dioxide liner, 13 a silicon dioxide layer was deposited on one side of a silicon wafer, as shown in Fig. 1.…”

Section: Sample Preparation and Synchrotron Xrd Measurementsmentioning

confidence: 99%

“…1. Vias were etched in the silicon wafer using anisotropic etching, followed by the etching of a group of microvias, called mesh, 13 in the suspended silicon dioxide layer at the base of the vias. Thermal oxidation was performed as a next step followed by a titanium-copper seed layer deposition over the silicon dioxide layer at the mesh end of the vias.…”

Section: Sample Preparation and Synchrotron Xrd Measurementsmentioning

confidence: 99%

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Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron x-ray diffraction

Liu

Thadesar

Taylor

et al. 2013

Journal of Applied Physics

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Strain measurements are demonstrated for through-silicon vias (TSVs) using synchrotron x-ray diffraction to characterize the effect of copper via dimensions and liner materials. Reduction in strains in the silicon around TSVs is observed for the TSVs with smaller via diameters and the TSVs with a thicker polymer liner. To interpret the measured two-dimensional (2D) TSV strain distribution maps of the three-dimensional (3D) TSV strains, a data averaging method based on the energy dependent x-ray absorption is implemented along with additional considerations from the sample preparation by means of an indirect comparison methodology. V

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Section: Sample Preparation and Synchrotron Xrd Measurementsmentioning

confidence: 99%

Section: Sample Preparation and Synchrotron Xrd Measurementsmentioning

confidence: 99%

Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron x-ray diffraction

Liu

Thadesar

Taylor

et al. 2013

Journal of Applied Physics

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“…As a consequence, the surface with the copper/titanium seed layer remains planarised. This approach with the thin bridge layer avoids the time-consuming and expensive polishing process to remove the thick overburden copper TSV hole sealing (normally thicker than 20 m) [10]. Aluminium interconnect is used in this process so the thin deposited copper electroplating seed layer and the over-plating domes are first removed before the aluminum is sputtered and patterned ( figure 7(g)).…”

Section: Test Chip Designmentioning

confidence: 99%

Test structures for electrical evaluation of high aspect ratio TSV arrays fabricated using planarised sacrificial photoresist

Zhang

Murray

et al. 2013

2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)

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An improved bottom-up electroplating technique has been successfully developed for the fabrication of TSV arrays with 9.5:1 aspect ratios. 125,500 TSVs have been fabricated in an area of 6×6 cm with a horizontal and vertical pitch of 240 m. A method of visually inspecting the via yield is presented, and Kelvin test structures and contact chain test structures have been fabricated to electrically evaluate single and multiple TSVs respectively. The average resistance of the Cu vias was measured as of 9.1 m using the Kelvin contact resistance structures.

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“…Then using anisotropic etching, TSVs are etched using a photoresist mask. After etching the vias, a mesh pattern is formed in the silicon dioxide suspended membrane on the back side of the vias [19]. Next, SU-8 is spin coated and optically defined using photolithography to obtain SU-8-clad vias.…”

Section: Ii: Polymer-clad Electrical Tsvsmentioning

confidence: 99%

Electrical, optical and fluidic through-silicon vias for silicon interposer applications

Parekh

Thadesar

Bakir

2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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Modern high-performance computing systems and data centers are implemented as many-core server systems. Current state of the art data centers have server racks with pluggable boards where each board has many multi-core processors and memory units. These boards are connected via electrical or optical cables. In such systems, communication bandwidth between the high-speed microprocessor cores and the memory is limited. To leverage full performance of these powerful chips, it is required to provide high memory bandwidth as well as effective power delivery and heat removal solutions. To address these challenges in high performance computing systems, we present a 3D packaging solution that includes a novel silicon interposer with electrical, optical, and fluidic (trimodal) interconnects and through-silicon vias (TSVs). The electrical TSVs in the silicon interposer enable power and signal delivery from motherboard to chips stacked on top of the interposer. The optical TSVs in the silicon interposer can provide ultra-high bandwidth communication between chips on different silicon interposers through motherboard level optical links. The fluidic TSVs enable a coolant to be routed from the motherboard to the chips on the silicon interposer. We have fabricated and characterized polymer-clad electrical TSVs (for low stress) with diameter that meets ITRS projections for high-performance computing systems. Using the same polymer used for the cladding of electrical TSVs, we have fabricated and characterized optical TSVs adjacent to electrical TSVs. Spin coating of the photodefinable polymer for electrical and optical TSVs is done in single step. Fabrication of fluidic TSVs can be done using the same cladding as that of the polymer-clad electrical TSVs without electroplating the copper. This leaves behind an empty polymer-clad via which can be used as a fluidic TSV. I: IntroductionThe performance of a processor is commonly measured as the number of instructions it processes per unit time. For high performance and utilization of the processor, the rate at which memory supplies instructions and data to the processor must match with the rate at which the processor is processing them. With the migration towards multi-core and multi-threading, the memory gap problem becomes more acute since now multiple processors on a single chip will increase the memory bandwidth demand. Thus, all the performance benefits of this processor cannot be fully leveraged because memory speeds are much slower compared to the processor speed [1, 2]. Fig. 1 shows scaling in processor frequencies and the memory speed over the past years. To solve this problem, we must improve the memory throughput and reduce the memory latency which includes interconnect delay in addition to memory access delay. This was quantified with analytical simulations to determine the effect of increased memory bandwidth on a processor chip, and we see that performance increase is proportional to the available memory bandwidth. Fig. 2 shows that throughput increases from 96 BIPS (bi...

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A ‘mesh’ seed layer for improved through-silicon-via fabrication

Cited by 19 publications

References 13 publications

Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron x-ray diffraction

Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron x-ray diffraction

Test structures for electrical evaluation of high aspect ratio TSV arrays fabricated using planarised sacrificial photoresist

Electrical, optical and fluidic through-silicon vias for silicon interposer applications

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