Test structures for electrical evaluation of high aspect ratio TSV arrays fabricated using planarised sacrificial photoresist

Abstract

An improved bottom-up electroplating technique has been successfully developed for the fabrication of TSV arrays with 9.5:1 aspect ratios. 125,500 TSVs have been fabricated in an area of 6×6 cm with a horizontal and vertical pitch of 240 m. A method of visually inspecting the via yield is presented, and Kelvin test structures and contact chain test structures have been fabricated to electrically evaluate single and multiple TSVs respectively. The average resistance of the Cu vias was measured as of 9.1 m using the Kelvin contact resistance structures.

Admittance extraction and analysis for through silicon vias near edge and at corner of silicon substrate

“…In real case, however, the silicon substrate has a limited size in both vertical and horizontal directions. For vertical direction, the finite thickness of the silicon substrate (or the TSV height) has an impact on the parasitic parameters of the TSVs, which have been studied in [7][8][9][10][11]. For horizontal direction, the finite edge length of silicon substrate may also affect parasitic parameters of TSVs due to different TSV distributions, as shown in Fig.…”