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Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such technologies are not suitable for highperformance chips due to ineffective power delivery and heat removal. This is important because high performance chips are projected to dissipate more than 100W/cm 2 and require more than 100A of supply current. Consequently, when such chips are stacked, the challenges in power delivery and cooling become greatly exacerbated. Thus, revolutionary interconnection and packaging technologies will be needed to address these limits [1]. This paper reports, for the first time, the configuration, fabrication, and experimental results of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for high-performance chips. The key behind this 3D platform is the ability to process integrate, at the wafer-level, electrical and microfluidic interconnection networks on the wafer containing the electrical circuitry and assemble such chips using conventional flip-chip technology.

In this work, the HfO2/Al2O3 multilayer structure is applied for RRAM arrays. Compared to HfO2 RRAM, the data retention failure of tail bits is suppressed significantly, especially for the high resistance state (HRS). The retention of tail bits is studied in detail by temperature simulation and crystallization analysis. We attribute the improvement of tail-bit retention to the decreased oxygen ion diffusivity caused by the Al2O3 layer. Furthermore, the HfO2/Al2O3 multilayer structure exhibits higher crystallization temperature, thus leading to fewer grain boundaries around the filament during the operations. With fewer grain boundaries, oxygen ion diffusion is suppressed, leading to fewer tail bits and better retention.

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