Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink

Dang, Bing; Bakir, Muhannad S.; Meindl, J.D.

doi:10.1109/led.2005.862693

Cited by 59 publications

(26 citation statements)

References 11 publications

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“…Although it is possible to introduce coolants within a thick 3D structure to handle very high power levels [35], such an approach is complex and requires thick cooling structures within the stack to bring in a sufficient fluid volume. Thus every effort should be made to remove heat from the back of a chip stack as is currently done for single high-power chips.…”

Section: Thermal Management and Effective Cooling Challengesmentioning

confidence: 99%

A Review of the Design Challenges for the 3-D on Chip Network Paradigms

Jain¹,

Patel²

2017

IJCA

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As feature sizes continue to shrink and integration densities continue to increase, interconnect delays have become a critical bottleneck in 2D NoC performance. The upcoming decades will require a change from mere transistor scaling to novel packaging architectures such as the vertical integration of chips referred as 3D integration. 3D silicon integration technologies have provided new opportunities for NoC architecture design in SoCs enabling the design of complex and highly interconnected systems in reduced space providing higher efficiency compared to 2D integration. The next challenge in front of researchers in the domain of NoC is to use NoC architecture as the backbone of the upcoming generation of 3D chips. Multiple design issues have to be addressed in this respect such as high chip temperature due to increasing power density leading to large interconnect-delays, lack of design methodologies, large area covered by vertical interconnects, problems related to optimally determining tier assignments and the placement of switches in 3D circuits. In this paper, we tried to exhibit and summarize the prevalent generic 3D NoC design issues highlighted by various recent research publications in the domain of NoC.

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Section: Thermal Management and Effective Cooling Challengesmentioning

confidence: 99%

A Review of the Design Challenges for the 3-D on Chip Network Paradigms

Jain¹,

Patel²

2017

IJCA

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“…The fluidic I/Os are implemented using surface-normal hollow-core polymer pins, or micropipes [28,29]. Unlike prior work on microfluidic cooling of ICs that require millimeter-sized and bulky fluidic inlets/outlets to the microchannel heat sink, the micropipe I/Os under consideration are microscale, wafer-level batch fabricated, area-array distributed, flip-chip compatible, and mechanically compliant.…”

Section: Novel Silicon Ancillary Technologiesmentioning

confidence: 99%

Power delivery, signaling and cooling for 2D and 3D integrated systems

Bakir

Huang

Dang

2010

Integrated Circuits and Systems

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“…In this case, the use of thermal vias to ensure adequate conductivity between the layers may need to be investigated. Since these cooling issues could place a significant design restriction on the types of systems that can be realized in a stacked configuration, conventional 2D cooling solutions will ultimately need to be replaced by 3D cooling solutions [32][33][34]. Such techniques that have been investigated in the literature include double-sided heat sinks, microchannels for fluidic cooling, and interleaved 3D heat-sink geometries.…”

Section: Challenges and Limitations For 3d Integrationmentioning

confidence: 99%

Wafer-level 3D integration technology

et al. 2008

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An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. IntroductionThe last few decades have seen an astonishing increase in the functionality of computational systems. This capability has been driven by the scaling of semiconductor devices, which has enabled the number of transistors on a single chip to grow at a geometric rate, following Moore's Law [1]. In particular, the scaling of silicon metal-oxide semiconductor field-effect transistors (MOSFETs) [2] drives the effort to continue this trend into the future.However, several serious roadblocks exist. The first is the difficulty and expense of continued lithographic scaling, which could make it economically impractical to scale devices beyond a certain pitch. The second is that even if lithographic scaling can continue, the power dissipated by the transistors will bring clock frequency scaling to a halt. In fact, it could be argued that clock frequency scaling has already stopped, and microprocessor designs have increasingly relied on new architectures to improve performance. These factors suggest that in the near future, it will no longer be possible to improve system performance through scaling alone, and that additional methods to achieve the desired enhancement will be needed. Three-dimensional (3D) integration technology offers the promise of being a new way of increasing system performance, even in the absence of scaling. This promise is due to a number of characteristic features of 3D integration, including decreased total wiring length (and thus reduced interconnect delay times), a dramatically increased number of interconnects between chips, and the ability to allow dissimilar materials, process technologies, and functions to be integrated. Motivation for 3D integration

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Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink

Cited by 59 publications

References 11 publications

A Review of the Design Challenges for the 3-D on Chip Network Paradigms

A Review of the Design Challenges for the 3-D on Chip Network Paradigms

Power delivery, signaling and cooling for 2D and 3D integrated systems

Wafer-level 3D integration technology

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