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Dealing with global on-chip memory allocation/de-allocation in a dynamic yet deterministic way is an important issue for upcoming billion transistor multiprocessor System-on-a-Chip (SoC) designs. To achieve this, we propose a new memory management hierarchy called Two-Level Memory Management. To implement this memory management scheme -which presents a paradigm shift in the way designers look at on-chip dynamic memory allocation -we present a System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation of the global on-chip memory, which we refer to as level two memory management (level one is the operating system management of memory allocated to a particular on-chip processor). In this way, heterogeneous processors in an SoC can request and be granted portions of the global memory in twenty clock cycles in the worst case for a four-processor SoC, which is at least an order of magnitude faster than software-based memory management. We present a sample implementation of the SoCDMMU and compare hardware and software implementations.

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Pervasive Computing is a very challenging and complex domain that still lacks a comprehensive unified architecture. In this paper, we propose a reference architecture for pervasive computing that captures most, if not all, of the key challenges and provides a new architecture model that can be used in almost any business context. It provides conceptual views for the smart environment (SE), the smart object (SO), and the pervasive system (PS). We evaluated the model using a simulation prototype to predict its reliability at runtime.

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