Embedded Hypervisor Xvisor: A Comparative Analysis

Patel, Anup; Daftedar, Mai; Shalan, Mohamed; El-Kharashi, M. Watheq

doi:10.1109/pdp.2015.108

Cited by 50 publications

(20 citation statements)

References 4 publications

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“…A prototype implementation of HyperMAMBO-X64 was built on top of the Linux Kernel Virtual Machine (KVM) [17] hypervisor. However the general concept is portable to other AArch64 hypervisors such as Xen [6] or Xvisor [28]. Another possibility for consumer devices such as smartphones, which do not need to run more than one OS, is to implement HyperMAMBO-X64 as part of a minimal hypervisor which only performs binary translation while allowing the guest OS full access to the underlying hardware.…”

Section: Methodsmentioning

confidence: 99%

HyperMAMBO-X64

d'Antras¹,

Gorgovan²,

Garside³

et al. 2017

Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

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Current computer architectures-ARM, MIPS, PowerPC, SPARC, x86-have evolved from a 32-bit architecture to a 64-bit one. Computer architects often consider whether it could be possible to eliminate hardware support for a subset of the instruction set as to reduce hardware complexity, which could improve performance, reduce power usage and accelerate processor development. This paper considers the scenario where we want to eliminate 32-bit hardware support from the ARMv8 architecture. Dynamic binary translation can be used for this purpose and generally comes in one of two forms: application-level translators that translate a single user mode process on top of a native operating system, and system-level translators that translate an entire operating system and all its processes. Application-level translators can have good performance but is not totally transparent; system-level translators may be 100% compatible but performance suffers. HyperMAMBO-X64 uses a new approach that gets the best of both worlds, being able to run the translator as an application under the hypervisor but still react to the behavior of guest operating systems. It works with complete transparency with regards to the virtualized system whilst delivering performance close to that provided by hardware execution. A key factor in the low overhead of HyperMAMBO-X64 is its deep integration with the virtualization and memory management features of ARMv8. These are exploited to support caching of translations across multiple address spaces while ensuring that translated code remains consistent with the source instructions it is based on. We show how these attributes are achieved without sacrificing either performance or accuracy.

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Section: Methodsmentioning

confidence: 99%

HyperMAMBO-X64

d'Antras¹,

Gorgovan²,

Garside³

et al. 2017

Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

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“…To enforce coloring in this way, one can leverage a lightweight partitioning hypervisor. A similar approach has been followed in [7], [9], [11], [12], that have considered Xvisor [13], KVM [14] and Jailhouse [15], respectively.…”

Section: A Background On the Jailhouse Partitioning Hypervisormentioning

confidence: 99%

The Potential of Programmable Logic in the Middle: Cache Bleaching

Roozkhosh

Mancuso

2020

2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in nextgeneration Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware redesigns, and by proposing software-only solutions to mitigate performance interference.Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach.

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“…Virtualisation for mobile devices is more relevant to this study, which has aroused increasing attention with the wide use of mobile devices and the fast evolution of ARM processors, but is still under development [54]. In the last few years, several studies have investigated the performance of virtualisation on different mobile devices, such as Raspberry PI 2 [55], Cubieboard2 [56], ARM Chromebook [57], Banana Pi [58], and Insignal Arndale board [59], and so on. However, since these studies were not directed to UAS, their performance analysis was limited to CPU, memory, and disk in a single device.…”

Section: Software Design For the Airborne Computing Platformmentioning

confidence: 99%