The Potential of Programmable Logic in the Middle: Cache Bleaching

Abstract

Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in nextgeneration Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware redesigns, and by proposing software-only solutions to mitigate performance interference.Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach.

Enzian: an open, general, CPU/FPGA platform for systems software research

“…This next experiment demonstrates the suitability of Enzian for prototyping custom memory controllers, such as PBerry [9], general physical memory manipulation, e.g., Cache Bleaching [58], as well as more general near-data processing. We demonstrate offloading a compute-intensive data reduction task: the colorspace transform and quantization part of a computer vision pipeline.…”

“…[18]) integrate CPU cores onto an FPGA die. Access to the cache protocol on the chip in these systems allows a use-case not possible with Intel HARP: the FPGA acting as part of the CPU's memory system, enabling research into new remote memory protocols [8,9] and cache management [58]. However, such systems are tiny in comparison with server machines, typically using 4 low-power ARM cores with limited DRAM.…”

Relational Memory: Native In-Memory Accesses on Rows and Columns

“…Traditionally, in PS-PL platform, the PL-side is used to map hardware accelerators that work in a load-unload fashion. However, Roozkhosh et al [58] have prompted a shift in paradigm with the introduction of the Programmable Logic in the Middle (PLIM) approach. This approach differentiates itself from the others in light of the way it considers and uses the PL-side.…”

“…This capability of inspecting memory traffic at the granularity of individual transactions has already been leveraged to address and tackle bedeviling problems. For instance, PLIM demonstrates how by simply manipulating each transaction address, memory fragmentation introduced by address coloring can be mitigated [58]. The same authors have also shown that the same type of module can be integrated in a wider framework in order to address the problem of memory traffic scheduling [33].…”

“…Specifically, we capitalize on recent advancements in reprogrammable hardware [58] that allow us to implement programmable logic between the memory and the processor. To ensure ease of programmability, we do not directly expose the specialized hardware to the data system engineer.…”