A reconfigurable, pipelined, conflict directed jumping search SAT solver

Safar, Mona; El-Kharashi, M. Watheq; Shalan, Mohamed; Salem, Ashraf

doi:10.1109/date.2011.5763199

Cited by 18 publications

(12 citation statements)

References 14 publications

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“…Our design implementation just occupies 4% of the Slice LUTs. In contrast to this, [12] requires 20 times more resources compared to SAT-Lancer, i.e., it occupies 80% of the overall Slice LUTs. These results clearly show that the proposed design is suitable for environments with limited HW-resources.…”

Section: Resultsmentioning

confidence: 80%

“…Such a SAT-instance represents a Boolean formula (coming from a verification task) and raises the question whether an assignment to all Boolean variables exists such that the overall formula is satisfied (SAT) or remains unsatisfied (UNSAT), respectively. Other existing approaches for SAT-solving either focus on accelerating a SW-based SAT-solver by outsourcing the solving process partially to HW [2,8,13,14] or by introducing even for small SAT-instance sizes a large HW-overhead [9,12]. In contrast to this, the proposed HW SAT-solver is very compact and can be easily integrated as an IP-component into an existing design.…”

Section: Introductionmentioning

confidence: 89%

“…SAT-Lancer has been written in Verilog. At first, the claimed compact character of SAT-Lancer is investigated by comparing the occupied HW-resources of our design against the implementation of [12]. Consequently, we implement our design on a Xilinx Virtex-II Pro FPGA as used in [12].…”

Section: Resultsmentioning

confidence: 99%

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SAT-Lancer

Ustaoglu

Huhn

Große

et al. 2018

Proceedings of the 2018 Great Lakes Symposium on VLSI

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To close the ever widening verification gap, new powerful solutions are strictly required. One such promising approach aims in continuing verification tasks after production of a chip during its lifetime. This approach is called self-verification. However, for realizing self-verification tasks on-chip, verification packages have to be developed. In this paper, we propose the verification package SATLancer. SAT-Lancer is a compact Boolean Satisfiability (SAT) solver and has been implemented entirely on HW with the capability of solving any arbitrary SAT-instance. At the heart of SAT-Lancer is a scalable memory model, which can be adjusted to given memory constraints and allows to store the SAT-instance most effectively. In comparison to previous HW SAT-solvers, SAT-Lancer utilizes significant less area and can handle order of magnitude larger SATinstances.

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Section: Resultsmentioning

confidence: 80%

Section: Introductionmentioning

confidence: 89%

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SAT-Lancer

Ustaoglu

Huhn

Große

et al. 2018

Proceedings of the 2018 Great Lakes Symposium on VLSI

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“…A complete SAT solver is implemented in hardware in [13]. Moving decision making and conflict analysis into hardware eliminates the communication latency between a software host and the hardware accelerator (we address this in section III).…”

Section: B Modern Hardware Sat Acceleratorsmentioning

confidence: 99%

FPGA acceleration of enhanced boolean constraint propagation for SAT solvers

Thong¹,

Nicolici²

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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We propose a hardware architecture to accelerate boolean constraint propagation (BCP). Although satisfiability (SAT) solvers in software use varying search and learning strategies, BCP is a fundamental component and by far consumes the most CPU time. Our field-programmable gate array (FPGA) design uses on-chip SRAM to facilitate the acceleration of BCP. We discuss many insights to our innovative hardware memory layout, which is very compact and enables extremely fast BCP. It also supports multithreading to minimize the idle time in hardware and to fully utilize the multicore processor host. Additionally, many industrial SAT instances encode logic gates as constraints. We compact these to simultaneously reduce the hardware memory usage as well as speed up the computation (enhanced BCP). We implemented our enhanced BCP core and integrated it with a simple software SAT solver which communicates over PCI Express. Hardware performance counters show that a single processing engine is up to 4x faster than a state-of-the-art software SAT solver.

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“…Several approaches based on complete algorithms have been proposed [12], [13]. The performance of recent complete algorithms [14]- [16] has been significantly improved by introducing several techniques to prune the search space [14]- [17].…”

Section: Related Workmentioning

confidence: 99%

An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA

Kanazawa

Matsumoto

2017

IEICE Trans. Inf. & Syst.

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SUMMARYWalkSAT (WSAT) is one of the best performing stochastic local search algorithms for the Boolean Satisfiability (SAT) and the Maximum Boolean Satisfiability (MaxSAT). WSAT is very suitable for hardware acceleration because of its high inherent parallelism. Formal verification of digital circuits is one of the most important applications of SAT and MaxSAT. Structural knowledge such as logic gates and their dependencies can be derived from SAT/MaxSAT instances generated from formal verification of digital circuits. Such that knowledge is useful to solve these instances efficiently. In this paper, we first discuss a heuristic to utilize the structural knowledge for solving these problems by using WSAT. Then, we show its implementation on FPGA. The problem size of the formal verification is typically very large, and most data have to be placed in offchip DRAMs. In this situation, the acceleration by FPGA is limited by the throughput and access latency of the DRAMs. In our implementation, data are carefully mapped on the on-chip memory banks and off-chip DRAMs so that most data in the off-chip DRAMs can be continuously accessed using burst-read. Furthermore, a variable-way cache memory comprised of the on-chip memory banks is used in order to hide the DRAM access latency by caching the head portion of the continuous read from the DRAMs and giving them to the circuit till the rest portion is started to be given by the burst-read. We evaluate the performance of our proposed method by changing configuration of the variable-way cache and the processing parallelism, and discuss how much acceleration can be achieved.

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A reconfigurable, pipelined, conflict directed jumping search SAT solver

Cited by 18 publications

References 14 publications

SAT-Lancer

SAT-Lancer

FPGA acceleration of enhanced boolean constraint propagation for SAT solvers

An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA

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