FPGA acceleration of enhanced boolean constraint propagation for SAT solvers

Abstract

We propose a hardware architecture to accelerate boolean constraint propagation (BCP). Although satisfiability (SAT) solvers in software use varying search and learning strategies, BCP is a fundamental component and by far consumes the most CPU time. Our field-programmable gate array (FPGA) design uses on-chip SRAM to facilitate the acceleration of BCP. We discuss many insights to our innovative hardware memory layout, which is very compact and enables extremely fast BCP. It also supports multithreading to minimize the idle time in hardware and to fully utilize the multicore processor host. Additionally, many industrial SAT instances encode logic gates as constraints. We compact these to simultaneously reduce the hardware memory usage as well as speed up the computation (enhanced BCP). We implemented our enhanced BCP core and integrated it with a simple software SAT solver which communicates over PCI Express. Hardware performance counters show that a single processing engine is up to 4x faster than a state-of-the-art software SAT solver.

SAT-Lancer

“…Such a SAT-instance represents a Boolean formula (coming from a verification task) and raises the question whether an assignment to all Boolean variables exists such that the overall formula is satisfied (SAT) or remains unsatisfied (UNSAT), respectively. Other existing approaches for SAT-solving either focus on accelerating a SW-based SAT-solver by outsourcing the solving process partially to HW [2,8,13,14] or by introducing even for small SAT-instance sizes a large HW-overhead [9,12]. In contrast to this, the proposed HW SAT-solver is very compact and can be easily integrated as an IP-component into an existing design.…”

Efficient Analog Circuits for Boolean Satisfiability

“…AC-SAT is also very competitive compared with existing hardware based approaches. For example, a recent work [29] reported a CPU+FPGA based MiniSat solver achieving ∼4X performance improvement over CPU based MiniSat. Since ASIC implementations typically achieves a maximum of 10X performance improvement over their FPGA counterparts [38], compared with a projected ASIC version of the FPGA design in [29], AC-SAT would still result in ∼600X or higher speedup.…”

“…For example, a recent work [29] reported a CPU+FPGA based MiniSat solver achieving ∼4X performance improvement over CPU based MiniSat. Since ASIC implementations typically achieves a maximum of 10X performance improvement over their FPGA counterparts [38], compared with a projected ASIC version of the FPGA design in [29], AC-SAT would still result in ∼600X or higher speedup. We do not directly compare with the custom digital IC in [30] since our simulation-based system cannot solve the large size problems considered in [30].…”

“…A number of hardware based SAT solvers have been proposed in the past. FPGAs based solutions have been investigated to accelerate the BCP part found in all "chafflike" modern SAT solvers [27]- [29]. Speedups of anywhere between 3X and 38X have been reported when comparing these FPGA based solvers over MiniSat [19], a well known, high-performance software solver.…”

“…Our simulations show that AC-SAT can significantly outperform (over tens of thousands times faster than) MiniSat, with the latter running on the latest, high-performance digital processors. For hard SAT problems with 50 variables and over 200 clauses, compared with the projected performance of a possible custom hardware implementation based a recent FPGA solver [29], AC-SAT offers more than ∼600X speedup. Monte Carlo simulations further demonstrate that AC-SAT is robust against device variations.…”