Building OpenLANE

Shalan, Mohamed; Edwards, Tim

doi:10.1145/3400302.3415735

Cited by 20 publications

(13 citation statements)

References 3 publications

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“…Verifications are performed at each stage to ensure the circuit's consistency with the original description. The outcome of the synthesis phase is a netlist that describes the connections between hardware primitives [19].…”

Section: Digital Asic Workflowmentioning

confidence: 99%

“…During signoff, a series of analyses are performed on the final design, including layout versus schematic (LVS), voltage drop (IR drop) analysis, and static timing analysis (STA). LVS verifies the circuit's integrity after component placement and routing, IR drop analysis assesses voltage level consistency across power lines, and STA evaluates circuit timing and the clock distribution network [19].…”

Section: Digital Asic Workflowmentioning

confidence: 99%

“…The open-source tool selected for the ASIC synthesis and layout design is the Open-LANE automated RTL to GDSII workflow [19]. This software routine utilizes custom scripts to bundle and automate the execution of a series of other open-source EDA tools, including OpenROAD [23], Yosys [24], Magic [25], Netgen [26], and KLayout [27].…”

Section: Open-source Eda Tool and Pdkmentioning

confidence: 99%

“…The SKY130 node is the most advanced opensource process design kit available online that an actual foundry can manufacture. The OpenLANE [19] open-source EDA tool handled the synthesis, optimization, and physical design phases of the ASIC workflow. The obtained final circuit is compatible with 32-bit microcontrollers and is optimized for a good frequency/area ratio.…”

Section: Introductionmentioning

confidence: 99%

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Custom ASIC Design for SHA-256 Using Open-Source Tools

Franck,

Ginja,

Carmo

et al. 2023

Computers

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The growth of digital communications has driven the development of numerous cryptographic methods for secure data transfer and storage. The SHA-256 algorithm is a cryptographic hash function widely used for validating data authenticity, identity, and integrity. The inherent SHA-256 computational overhead has motivated the search for more efficient hardware solutions, such as application-specific integrated circuits (ASICs). This work presents a custom ASIC hardware accelerator for the SHA-256 algorithm entirely created using open-source electronic design automation tools. The integrated circuit was synthesized using SkyWater SKY130 130 nm process technology through the OpenLANE automated workflow. The proposed final design is compatible with 32-bit microcontrollers, has a total area of 104,585 µm2, and operates at a maximum clock frequency of 97.9 MHz. Several optimization configurations were tested and analyzed during the synthesis phase to enhance the performance of the final design.

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Section: Digital Asic Workflowmentioning

confidence: 99%

Section: Digital Asic Workflowmentioning

confidence: 99%

Section: Open-source Eda Tool and Pdkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Custom ASIC Design for SHA-256 Using Open-Source Tools

Franck,

Ginja,

Carmo

et al. 2023

Computers

View full text Add to dashboard Cite

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“…There have been eleven tape-outs based on Chisel utilizing the Rocket-chip generator [12] by the University of California, Berkeley but were based on commercial EDA tools and closed PDKs. Also, a family of striVe SoCs was taped out using the OpenLANE and Skywater 130nm PDK to prove the viability of all open-source EDA tools and the PDK [13]. However, it is written in a traditional low-level hardware description language, Verilog.…”

Section: Previous Workmentioning

confidence: 99%

IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip

Khan¹,

Jalal²,

Ahmed³

et al. 2021

Preprint

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Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

Pandey

Shrimali

2022

IEEE Access

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Parallelism is the key to enhancing the throughput of computing structures. However, it is well established that the presence of data-flow dependencies adversely impacts the exploitation of such parallelism. This paper presents a case for a new computing paradigm namely subscalar digital arithmetic which is aimed at mitigating this issue. It proposes to break up atomic data and atomic operations thereon into sub-atomic data fragments and sub-atomic partial operations. Such a break-up exposes hitherto unexploited levels of parallelism by way of allowing overlap of operations even if data-dependent. Surprisingly this enhanced exploitation of latent parallelism comes with a favorable impact on the area-power characteristics of corresponding computing structures which is contrary to common sense. The paper also proposes a novel micro cell library with logic primitives at corresponding subscalar levels. The synthesized circuits for several sequential benchmarks show an order of magnitude improvement in their area-throughput figure-of-merit (FOM).INDEX TERMS Bit-level parallelism, digital arithmetic, pipelining.

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Building OpenLANE

Cited by 20 publications

References 3 publications

Custom ASIC Design for SHA-256 Using Open-Source Tools

Custom ASIC Design for SHA-256 Using Open-Source Tools

IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

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