Custom ASIC Design for SHA-256 Using Open-Source Tools

Abstract

The growth of digital communications has driven the development of numerous cryptographic methods for secure data transfer and storage. The SHA-256 algorithm is a cryptographic hash function widely used for validating data authenticity, identity, and integrity. The inherent SHA-256 computational overhead has motivated the search for more efficient hardware solutions, such as application-specific integrated circuits (ASICs). This work presents a custom ASIC hardware accelerator for the SHA-256 algorithm entirely created using open-source electronic design automation tools. The integrated circuit was synthesized using SkyWater SKY130 130 nm process technology through the OpenLANE automated workflow. The proposed final design is compatible with 32-bit microcontrollers, has a total area of 104,585 µm2, and operates at a maximum clock frequency of 97.9 MHz. Several optimization configurations were tested and analyzed during the synthesis phase to enhance the performance of the final design.

Design and Test of Offset Quadrature Phase-Shift Keying Modulator with GF180MCU Open Source Process Design Kit

“…Its modular approach and portability support innovation and experimentation in the field of circuit and integrated system design. 2023) developed an application-specific IC (ASIC) accelerator for secure hash algorithm-2 (SHA)-256 using open source electronic design tools and SkyWater's 130 nm technology [23], standing out for its optimization and compatibility with 32-bit microcontrollers. Shah et al (2023) presented FABulous [24], an open and highly customizable FPGA fabric generator, demonstrated on the first silicon manufactured in the open Skywater 130 nm PDK, sponsored by Google.…”