A dynamic memory management unit for embedded real-time system-on-a-chip

Shalan, Mohamed; Mooney, Vincent J.

doi:10.1145/354880.354905

Cited by 33 publications

(14 citation statements)

References 11 publications

(8 reference statements)

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“…Bai et al [4] looked at heap-data management for SPMs. Shalan et al [34] looked at dynamic memory management for global memory through the use a hardware module.…”

Section: Related Workmentioning

confidence: 99%

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

Bathen

Shin

Lim

et al. 2013

Des Autom Embed Syst

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Emerging multicore platforms are increasingly deploying distributed scratchpad memories to achieve lower energy and area together with higher predictability; but this requires transparent and efficient software management of these critical resources. In this paper, we introduce the concept of ScratchPad Memory virtualization, a hardware/software run-time layer (called SPMVisor) that virtualizes the scratchpad memory space in order to facilitate the use of distributed SPMs in an efficient, transparent and secure manner. We introduce the notion of virtual scratchpad memories (vSPMs), which can be dynamically created and managed as regular SPMs. The SPMVisor exploits policy-driven allocation strategies based on application privilege levels and data level prioritization metrics (e.g., utilization) to efficiently manage the on-chip memory real-estate. Our experimental results on Mediabench/CHStone benchmarks running on various Chip-Multiprocessor configurations and software stacks (RTOS, virtualization, secure execution) showed that SPMVisor enhances performance by 71 % on average and reduces power consumption by 79 % on average with respect to traditional context switching schemes. We showed the benefits of using vSPMs in a various environments (a RTOS multi-tasking environment, a virtualization environment, and a trusted execution environment). Furthermore, we explored the effects of mapping instructions and data onto vSPMs, and showed that sharing on-chip space reduces both execution time and energy by an average 16 % and 12 % respectively. We then compared our priority-driven memory allocation scheme with traditional dynamic allocation and showed an average 54 % execution time reduction and 65 % energy savings. Finally, to further validate the SPMVisor's benefits, we modified the initial bus-based architecture to include a mesh-based CMP with up to 4 × 4 nodes. We were able to observe that SPMVisor's priority-driven allocator was able to reduce execution time by an average 17 % with respect to competing allocation policies, while saving an average 65 % across various architectural configurations. We were also able to observe that SPMVisor reduces execution time by an average 12.6 % with respect to competing allocation policies, while saving an average 63.5 % in total energy for various architectural configuration running 1024 jobs.

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“…Bai et al [4] looked at heap-data management for SPMs. Shalan et al [34] looked at dynamic memory management for global memory through the use a hardware module.…”

Section: Related Workmentioning

confidence: 99%

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

Bathen

Shin

Lim

et al. 2013

Des Autom Embed Syst

View full text Add to dashboard Cite

show abstract

“…In [17] and [3], the authors propose a memory allocator/deallocator (namely, SoCDMMU) suitable for real-time systems. The main characteristic is that, by using the SoCD-MMU, the memory management is fast and deterministic.…”

Section: Related Workmentioning

confidence: 99%

Exploration of distributed shared memory architectures for NoC-based multiprocessors

Monchiero

Palermo

Silvano

et al. 2007

Journal of Systems Architecture

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“…The authors of [54] present a deterministic hardware-based dynamic memory manager. The memory is hierarchically managed.…”

Section: Enforcing Runtime Policiesmentioning

confidence: 99%

“…Moreover, all our custom DM managers are implemented in the middleware on top of the Operating System, hence platform independent. This means that they do not require any hardware changes, as opposed to [54].…”

Section: Existing Memory Managers Focus On Different Parts Of the Desmentioning

confidence: 99%

Power-efficient data management for dynamic applications

Marchal

Perez

Atienza

et al. 2006

System-on-Chip: Next Generation Electronics

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multi-processor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility also perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads running on the different processors into account, only locally optimize the bandwidth nor deal with the dynamic behavior of these applications. The contributions of this chapter are to outline the main limitations of current techniques and to introduce an approach for dealing with the dynamic multi-threaded of our application domain. The design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [53]. These systems require an enormous computational performance (40GOPS 1 ). Even though current PCs offer this performance requirement, they consume too much power (10-100W). Mobile devices should consume at least two or three orders of magnitude less power [30]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. The era of platform-based designA platform is a fixed micro-architecture together with a programming environment that minimizes mask-making costs and is flexible enough to work for a set of applications [4]. The production volumes can then remain high over an extended chip lifetime.Given the strong energy constraints, we must choose the flavor of these platforms. Since power is cubic to the processing frequency, parallelism is an effective to reduce power and energy consumption. Then, multiple simple processors are preferred to one complex speculative and out-of-order processor. In the right application domain, we can get better performance and spend less energy. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a Digital Signal Processor (DSP). The RISC is more energy-efficient for the input/output processing and simple control-dominated 1 Giga Operations Per Second

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A dynamic memory management unit for embedded real-time system-on-a-chip

Cited by 33 publications

References 11 publications

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

Exploration of distributed shared memory architectures for NoC-based multiprocessors

Power-efficient data management for dynamic applications

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