Abstract-Application-specific multiprocessor systems-on-chip (MPSoCs) are usually designed by using a platform-based approach, where a wide range of customizable parameters can be tuned to find the best tradeoff in terms of the selected figures of merit (such as energy, delay, and area). This optimization phase is called design space exploration (DSE), and it usually consists of a multiobjective optimization problem with multiple constraints. So far, several heuristic techniques have been proposed to address the DSE problem for MPSoC, but they are not efficient enough for managing the application-specific constraints and for identifying the Pareto front. In this paper, an efficient DSE methodology for application-specific MPSoC is proposed. The methodology is efficient in the sense that it is capable of finding a set of good candidate architecture configurations by minimizing the number of simulations to be executed. The methodology combines the design of experiments (DoEs) and response surface modeling (RSM) techniques for managing system-level constraints. First, the DoE phase generates an initial plan of experiments used to create a coarse view of the target design space to be explored by simulations. Then, a set of RSM techniques is used to refine the simulation-based exploration by exploiting the application-specific constraints to identify the maximum number of feasible solutions. To trade off the accuracy and efficiency of the proposed techniques, a set of experimental results for the customization of a symmetric shared-memory on-chip multiprocessor with actual workloads has been reported in this paper.

Since the mid-1990s, researchers have been trying to use machine-learning based approaches to solve a number of di erent compiler optimization problems. These techniques primarily enhance the quality of the obtained results and, more importantly, make it feasible to tackle two main compiler optimization problems: optimization selection (choosing which optimizations to apply) and phase-ordering (choosing the order of applying optimizations). The compiler optimization space continues to grow due to the advancement of applications, increasing number of compiler optimizations, and new target architectures. Generic optimization passes in compilers cannot fully leverage newly introduced optimizations and, therefore, cannot keep up with the pace of increasing options. This survey summarizes and classi es the recent advances in using machine learning for the compiler optimization eld, particularly on the two major problems of (1) selecting the best optimizations, and (2) the phase-ordering of optimizations. The survey highlights the approaches taken so far, the obtained results, the ne-grain classi cation among di erent approaches and nally, the in uential papers of the eld. A. H. Ashouri et al.unrolling, register allocation, etc.) could substantially bene t several performance metrics. Depending on the objectives, these metrics could be execution time, code size, or power consumption. A holistic exploration approach to trade-o these metrics also represents a challenging problem [193].Autotuning [35,256] addresses automatic code-generation and optimization by using di erent scenarios and architectures. It constructs techniques for automatic optimization of di erent parameters to maximize or minimize the satis ability of an objective function. Historically, several optimizations were done in the backend where scheduling, resource-allocation and code-generation are done [56,93]. The constraints and resources form a linear system (ILP) which needs to be solved. Recently, researchers have shown increased e ort in introducing front-end and IR-optimizations. Two observations support this claim: (1) the complexity of a backend compiler requires exclusive knowledge strictly by the compiler designers, and (2) lower overheads with external compiler modi cation compared with back-end modi cations. The IR-optimization process normally involves ne-tuning compiler optimization parameters by a multi-objective optimization formulation which can be harder to explore. Nonetheless, each approach has its bene ts and drawbacks and are subject to analysis under their scope.A major challenge in choosing the right set of compiler optimizations is the fact that these code optimizations are programming language, application, and architecture dependent. Additionally, the word optimization is a misnomer -there is no guarantee the transformed code will perform better than the original version. In fact, aggressive optimizations can even degrade the performance of the code to which they are applied [251]. Understanding the behavior of the optimization...

The microprocessor architecture transition from multi-core to many-core will drive increased chip-to-chip I/O bandwidth demands at processor/memory interfaces and in multi-processor systems. Future architectures will require bandwidths of 200GB/s to 1.0TB/s and will bring about the era of tera-scale computing. To meet these bandwidth demands, traditional electrical interconnect techniques require increases in circuit complexity and costlier materials. However, without lower loss electrical interconnects, this method of increasing I/O bandwidth in electrical links eventually comes at the cost of reducing interconnect link length, reducing signal integrity or increasing power consumption. Optical interconnect with its terahertz bandwidth, low loss, and low cross-talk has been proposed to replace electrical interconnect between chips [1]. This paper describes results for both near and long-term chip-to-chip optical interconnect architectures.The near-term approach is a single package "hybrid" implementation [2] which avoids complex chip carrier packaging [3] and uses CMOS optical transceivers that are compatible with future integration in a microprocessor or logic die. Figure 28.1.1 shows the hybrid optical I/O package architecture that allows for up to 12 optical transmit or receive channels per optical connector. Linear 1×12 arrays of GaAs VCSELs and detectors are flip-chip bonded to the package substrate and polymer waveguides with 45°mirrors are embedded in the package substrate. In order to obtain adequate electrical signal integrity, the high-speed lines, which connect the VCSEL (photodiode) bumps to the transceiver chip's I/O bumps, are routed on the substrate surface as controlled 50Ω impedance microstrip traces. This avoids impedance discontinuities, while the close proximity between the transceiver chip and the optical elements minimizes frequency dependent loss. Power and bias planes are incorporated into the substrate to bias the optical elements.An 8 channel prototype chip, shown in Fig. 28.1.7, was implemented in 90nm CMOS and includes 16 cells with VCSEL drivers, TIA receivers, and clock-data recovery ( Fig. 28.1.2), which can be configured individually as optical TX/RX. The fully packaged prototype achieves open transmit and receive eye diagrams at up to 10Gb/s (Fig. 28.1.3). Higher data rates are possible with a combination of future packaging refinements aimed at reducing TIA input capacitance and circuit techniques, which extend VCSEL bandwidth. Electrical probe measurements of the TIA, which uses cross-coupled cascodes to boost gain and bandwidth [4], yields open eye diagrams at 12.5Gb/s and 18Gb/s with input capacitance of 260fF and 90fF, respectively. Implementing sub-bit interval pre-emphasis in the transmitter [4] allows for 18Gb/s operation with 122% vertical and 76% horizontal eye opening improvement with a 10Gb/sclass VCSEL. The optical receiver and driver energy efficiency is 11pJ/b at 10Gb/s, including the 38mW TIA/limiting amplifier and a reduced power 72mW transmitter that excludes pr...

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