ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration

Abstract

Abstract-Application-specific multiprocessor systems-on-chip (MPSoCs) are usually designed by using a platform-based approach, where a wide range of customizable parameters can be tuned to find the best tradeoff in terms of the selected figures of merit (such as energy, delay, and area). This optimization phase is called design space exploration (DSE), and it usually consists of a multiobjective optimization problem with multiple constraints. So far, several heuristic techniques have been proposed to address the DSE problem for MPSoC, but they are not efficient enough for managing the application-specific constraints and for identifying the Pareto front. In this paper, an efficient DSE methodology for application-specific MPSoC is proposed. The methodology is efficient in the sense that it is capable of finding a set of good candidate architecture configurations by minimizing the number of simulations to be executed. The methodology combines the design of experiments (DoEs) and response surface modeling (RSM) techniques for managing system-level constraints. First, the DoE phase generates an initial plan of experiments used to create a coarse view of the target design space to be explored by simulations. Then, a set of RSM techniques is used to refine the simulation-based exploration by exploiting the application-specific constraints to identify the maximum number of feasible solutions. To trade off the accuracy and efficiency of the proposed techniques, a set of experimental results for the customization of a symmetric shared-memory on-chip multiprocessor with actual workloads has been reported in this paper.

Knowledge-based design space exploration of wireless sensor networks

“…The distance between the Pareto sets have been compared using the Average Distance from Reference Set (ADRS) [17]. The ADRS is usually measured in terms of percentage and should be minimized.…”

“…For each state in s, all possible actions are applied, generating the configurations that differ from s0 by one parameter (lines [13][14][15][16][17][18][19][20][21][22][23][24][25][26]. For all the generated configurations (obtained by applying a in si), s k metrics are partitioned, D and T P (si, a, s k ) are updated.…”

Low Effort Design Space Exploration Methodology for Configurable Caches

“…To adhere to the application hardware requirements, much prior research focused on configurable hardware (e.g., [13][14][15][16][17][18][19][20][21][22][23]), configurable caches (e.g., [3,4,[24][25][26][27]), and design space exploration (e.g., [5][6][7][9][10][11][28][29][30][31][32]). Given this expansive prior work, we discuss fundamentals of configurable hardware, followed by specific related work in configurable caches and design space exploration with fundamentals that are directly applicable to our approach.…”

“…The results revealed that a subset of size 4 (out of 18) configurations provided energy savings within 1% and 5% of the complete design space for the instruction and data cache, respectively. Palermo et al [29] developed a methodology that iteratively eliminated the evaluated configurations from the design space. On each iteration, a set of Pareto configurations was selected.…”

Supervised design space exploration by compositional approximation of Pareto sets

“…The third category is based on estimating metrics of interest under given configurations, as opposed to actually running time-consuming simulation or synthesis. Example estimators include Fuzzy Systems [2], Markov Decision Process [4], and response surface modeling [17]. These approaches cannot work alone and should be incorporated with optimization frameworks.…”