AES power attack based on induced cache miss and countermeasure

Abstract

Abstract

A Cache Timing Analysis of HC-256

“…Subsequent research verified the correctness of the findings [11,10,9,15], improved the attack technically [14,3,8] or algorithmically [5], and devised and analysed countermeasures [6,4,16].…”

“…Obviously, these requirements are not always met. However, they are relevant in shared server and in sandbox scenarios, and Bertoni et al [3] show how to use cache timings if the adversary has physical access to a device, making the attack much more realistic.…”

Cache Based Power Analysis Attacks on AES

“…In order for the cache to reveal information as described above, enough time needs to have passed between the execution of Algorithm 3 and the ciphering algorithm so that the cache no longer contains the randomised look-up table. In theory, it may be possible to apply the attack in [3] but it is necessary to know the cache lines that no longer contain the randomised look-up table.…”

“…Several attacks have been published on using cache access events as a sidechannel [2,3,11,16] on DES and AES. These are predominately timing attacks taking into account the total number of cache misses in the algorithm to determine information on the secret key being used.…”

A comprehensive study of multiple deductions-based algebraic trace driven cache attacks on AES

“…Cache attacks demonstrated fall into three categories, depending on the channels used to collect the leakages. These channels are spy processes [1], timing information [2,3] and power/electromagnetic (EM) traces [4,5,6,7,8,9,10,11]. The focus of this paper is trace driven cache attack (TDCA), which exploits the power or electromagnetic traces.…”