A security monitoring service for NoCs

Fiorin, Leandro; Palermo, Gianluca; Silvano, Cristina

doi:10.1145/1450135.1450180

Cited by 64 publications

(46 citation statements)

References 11 publications

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“…However, during an attack, a significant percent of PAPs are expected to have a higher NLD. We clearly see this contrast in an attack scenario, where more than 60% of packets have an NLD greater than the chosen NLD (12). Hence, there is a clear separation between a no-attack and attack scenario that enables the identification of a trojan.…”

Section: Rlan Efficacymentioning

confidence: 89%

“…Diguet et al's work on SNI can protect from denial of service (DoS) attack caused by replay, livelock, deadlock, and incorrect path. Fiorin et al propose the use of DoS probe as a part of the NoC monitoring architecture [12]. Parallel to these works in security, there have been numerous proposals to provide quality of service (QoS) guarantees in a NoC [9].…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Security Measures Against a Rogue Network-on-Chip

et al. 2017

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Network-on-chip facilitates glueless interconnection of various on-chip components in the forthcoming system-on-chips. As in the case of any new technology, security is a major concern in network-on-chip (NoC) design too. In this work, we explore a covert threat model for multiprocessor system-on-chips (MPSoCs) stemming from the use of malicious third-party network-on-chips (NoCs). We illustrate that a rogue NoC (rNoC) can selectively disrupt the perceived availability of on-chip resources, thereby causing large performance bottlenecks for the applications running on the MPSoC platform. Further, to counter the threat posed by rNoC, we propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. We also discuss measures that can be taken to minimize the impact of a rNoC, once it is detected. Our comprehensive cross-layer analysis of our novel detection technique indicates modest overheads of 12.73% in area, 9.844% in power, and 5.4% in terms of network latency.

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Section: Rlan Efficacymentioning

confidence: 89%

Section: Related Workmentioning

confidence: 99%

Security Measures Against a Rogue Network-on-Chip

et al. 2017

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“…• If an on-chip security sensor detects suspected tampering [12], messages can be sent to all processor cores protecting their memory and processing in a timely fashion. • In the event of a voltage droop in a specific core, information about the droop can be quickly sent to other cores so residual effects can be monitored and addressed.…”

Section: B Sensor Data Broadcasting Applicationsmentioning

confidence: 99%

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

Zhao

Burleson

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Contemporary multi-core architectures deployed in embedded systems are expected to function near the operational limits of temperature, voltage, and device wear-out. To date, most on-chip sensing systems have been designed to collect and use sensor information for these parameters locally. In this paper, a new sensing system to enhance multi-core dependability which supports both the local and global distribution of sensing data in embedded processors is considered. The benefit of the new sensing architecture is verified using the broadcast of microarchitectural parameter signatures which can be used to identify impending voltage droops. Low-latency broadcasts are supported for a range of sensor data transfer rates. Up to a 9% performance improvement for a 16-core system is determined via the use of the distributed voltage droop sensor information (5.4% on average). The entire sensing system, including broadcasting resources, requires about 2.6% of multi-core area.

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“…The concept and architectures are proven by gate-level implementation and gate-level signal traces. Fiorin et al [12] have detailed a security monitoring system for NoC based architectures. The proposed architecture is composed of probes and a Network Security Manager (NSM).…”

Section: Related Workmentioning

confidence: 99%

Run-Time Monitoring Mechanism for Efficient Design of Application-Specific NoC Architectures in Multi/Manycore Era

Ahmed

Ochi

Miura

et al. 2013

2013 Seventh International Conference on Complex, Intelligent, and Software Intensive Systems

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One of the major design challenges of Networkon-Chip interconnect is the storage buffers. They occupy a significant portion of the system's area and so they are considered as main "power-hungry" components. Deciding the appropriate buffers size and implementation in these systems is the key technique for increasing system performance and also for reducing overall area and power consumption. However, this goal is very hard to achieve with traditional design approaches, where design decisions of the main architectural parameters are generally made with slow and inaccurate software simulation or theoretical modeling. In order to quickly capture and decide the optimal buffers size and the whole system behavior, we propose in this work an efficient design method for Network-on-Chip architecture based on a novel run-time monitoring mechanism (RMM). The system monitors the traffic flow at different system's resources and sends the monitored run-time traffic information to a specialized controller. In addition, our proposed design method allows to easily compute optimal architecture hardware parameters (i.e Buffer size) and allocate the appropriate values on demand to satisfy the requirements of any given application. The RMM mechanism was designed in hardware and integrated into our NoC system (PNoC) 1 . From the evaluation results, we conclude that the system performance in terms of execution time was about 27% better when compared with traditional design methods over several benchmark programs.

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A security monitoring service for NoCs

Cited by 64 publications

References 11 publications

Security Measures Against a Rogue Network-on-Chip

Security Measures Against a Rogue Network-on-Chip

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

Run-Time Monitoring Mechanism for Efficient Design of Application-Specific NoC Architectures in Multi/Manycore Era

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