SummaryStatic random access memory (SRAM)‐based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems. Several SRAM cells had been developed to address the stability and power loss problem. But still, it is a challenge to achieve balance performance among all the parameters of the SRAM cell for sub‐nanometer technology. This paper proposes a novel SRAM cell, which is having comparatively less total, static power loss, less delay, and high stability compared with the conventional cells for 45‐nm complementary metal‐oxide‐semiconductor (CMOS) technology. The total power cost of the proposed 10T cell has been reduced by 90.3%, 85.84%, 51.02%, and 90.9% compared with 6T, N‐controlled (NC), 10T sub, and 10T, respectively. Similarly, the static power cost of the proposed cell has been reduced by 55.17%, 5.72%, ‐41.6%, and 52.9% compared with 6T, NC, 10T‐sub, and 10T, respectively. The proposed cell provides better stability, less delay, and comparable area compared with other considered 10T cells. Finally, the Monte Carlo (MC) simulation and process analysis of SRAM cells validate the efficiency of the proposed 10T cell.

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Memory is an essential component of any VLSI data storage system. Because of the shrinking of CMOS processing nodes, power consumption in conventional memory (SRAM and DRAM) increases. Traditional memory technologies also suffer several additional difficulties, such as limited scalability, low reliability, short data retention time, low durability, increased space, and latency, among others. As a result, new device technologies are critical for developing low-power, high-performance memory devices. Among the numerous developing nonvolatile (NV) memory technologies available today, STT-MRAM is regarded as one of the most appealing and promising NV memory technologies for overcoming the limitations of traditional memories. STT-MRAM is more efficient, quicker, NV, highly scalable, and readily integrated with CMOS technology. Because of the scalability of technology nodes below 45 nm, traditional STT-MRAM cells have several difficulties, including high write power consumption, destructive read and write operation, prolonged write time, and so on. To address the issues associated with the writing operation of STT-MRAM cells, this article presented an optimum STT-MRAM cell design based on PMA-MTJ. The write failure mitigation strategies are utilized to increase the proposed cell's write stability. A comparative analysis between conventional STT-MRAM cell and the proposed cell is performed by concerning the write power consumption, write delay, and write stability. The experimental results indicate the performance superiority of the proposed cell architecture.IP (in-plane), MTJ (magnetic tunnel junction), PMA (perpendicular magnetic anisotropy), STT-MRAM, write margin, write power | INTRODUCTIONSemiconductor memory devices and technologies, such as memory storage, are critical for data storage in electronics. Memory currently occupies more than 80% of the die area. This percentage is constantly increasing due to the continued reduction of the CMOS technology node below the 90-nm domain. Memory performance rises in terms of size and speed owing to technological scaling, while the static power consumption of CMOS-based memories increases due to an exponential growth in standby current. 1 Memory reliability is also impacted. The length of global interconnects