SummaryStatic random access memory (SRAM)‐based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems. Several SRAM cells had been developed to address the stability and power loss problem. But still, it is a challenge to achieve balance performance among all the parameters of the SRAM cell for sub‐nanometer technology. This paper proposes a novel SRAM cell, which is having comparatively less total, static power loss, less delay, and high stability compared with the conventional cells for 45‐nm complementary metal‐oxide‐semiconductor (CMOS) technology. The total power cost of the proposed 10T cell has been reduced by 90.3%, 85.84%, 51.02%, and 90.9% compared with 6T, N‐controlled (NC), 10T sub, and 10T, respectively. Similarly, the static power cost of the proposed cell has been reduced by 55.17%, 5.72%, ‐41.6%, and 52.9% compared with 6T, NC, 10T‐sub, and 10T, respectively. The proposed cell provides better stability, less delay, and comparable area compared with other considered 10T cells. Finally, the Monte Carlo (MC) simulation and process analysis of SRAM cells validate the efficiency of the proposed 10T cell.

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A pulse skipping modulation (PSM) technique improves the light load efficiency in a DC-DC converter by selectively skipping a few clock pulses. However, in existing PSM schemes, the number of charge and/or skipped cycles cannot be pre-defined. Therefore it is difficult to predict the ripple parameters and ensure a stable periodic behavior. Further it becomes difficult to further minimize power losses under light load conditions. This paper proposes a voltage-mode digital pulse skipping modulator which uses a digital pulse-width-modulator (PWM) as a building block, thus making it easy to operate the system in both PWM and PSM modes. Unlike in existing PSM schemes, the sequence and the count of charge and skip cycles can be fully pre-specified in the proposed scheme, with the number of skip cycles optimally chosen to maximize the efficiency. Stability analysis is carried out using discrete-time modeling, which provides guidelines to ensure a stable periodic operation with predictable ripple parameters. Small-signal modeling and design of the proposed PSM scheme are discussed. A prototype buck converter was fabricated and tested. The proposed control scheme is implemented using an FPGA device, and the experimental results fully support the analytical predictions.

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Pulse skipping modulation (PSM) helps to improve the light-load efficiency in a DC-DC converter with a stable periodic behaviour and predictable ripple parameters. A periodic steady-state operation under PSM consists of a charge pulse followed by a pre-defined count of skipped pulses, where individual pulses are referred to a fixed-frequency clock with a time period T. Thus the overall time period is simply the total count of pulses times the time period T, and the power spectrum is distributed accordingly. Although the light-load efficiency improves by increasing the number of skipped cycles, the count is limited by the specified output voltage ripple. This paper introduces a novel concept of fractional pulse skipping in a digitally controlled PSM DC-DC converter, which improves the power spectrum, without degrading the efficiency and violating the ripple constraint. In the proposed PSM, the number of charge and skipped cycles can be fully customized and the skipped cycle count needs to be periodically varied. The proposed PSM uses an existing digital-pulse-width-modulator (DPWM) architecture and adds extra features with only a little modification. Thus a seamless PSM/PWM transition can be inherently achieved. Stability analysis is carried out using discrete-time models and design guidelines are presented. The proposed scheme is implemented using an FPGA device and tested in a mixed-signal current-mode DPWM buck converter.978-1-4673-9550-2/16/$31.00 ©2016 IEEE

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