Design and statistical analysis of low power and high speed 10T static random access memory cell

Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

Section: Simulation Results and Discussionmentioning

confidence: 99%

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

“…Due to the voltage division effect in the read path, a nonzero voltage is developed at the "0"-storing node(s), which can flip the stored data during read operation. Conventionally, read stability is estimated using the read static noise margin (RSNM), [23][24][25] which is estimated as the side length of the largest square that can be inserted in the smallest lobe of the butterfly curve (Figure 4B). 1 If a cell has a lower CR, a higher voltage is developed at the "0"-storing node(s).…”

Section: Read Stability Comparisonmentioning

confidence: 99%

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Pal

Divya

et al. 2021

In advanced technology, static random-access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high-energy particle strikes, which cause soft-error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation-hardened readdecoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read-decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02Â/1.06Â/1.07Â/1.08Â over NS10T/RHD12T/PS10T/RHBD10T at V DD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single-event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. K E Y W O R D Sdigital circuit, low power design, memory design, read stability, SRAM | INTRODUCTIONSatellites have become an integral part of human society, as we rely on satellite communication for a wide range of services, from meteorology to disaster monitoring, from navigation systems to military operations, and so on. 1 As the technology is advancing, lightweight satellites are replacing heavyweight satellites because of their higher manufacturing cost. 2 Since lightweight satellites have limited resources, they require high-density memory cells, and static random-access memory (SRAM) cells are the best alternative for space applications because of their high packing density and improved logic performance. 1 Space presents extreme conditions, like temperature fluctuations and radiation. Due to the weak geomagnetic field in space, radiation and energized particles increase. To withstand this harsh environment, special electronic components and circuits are used. Once a radiation particle strikes a logic circuit at its sensitive node, it generates electron-hole pairs (Figure 1A). These pairs become separated and accumulate at the sensitive node. 3 The accumulated charge at the sensitive node then generates a transient voltage pulse. If enough charge (i.e., critical charge, Q C ) is

“…The RSNM is graphically measured as the side length of the largest square that can be inserted inside the smaller lobe of the read butterfly curve. 6,31,32 To plot the butterfly curve of the proposed design during the read operation, the cell should be placed in the read mode. Therefore, BL is precharged to V DD , and RWL is pulled up.…”

Section: Read Stabilitymentioning

confidence: 99%

“…The write-ability of an SRAM cell is characterized by WSNM and depicts its ability to pull down the node storing "1" to a voltage below the switching threshold of the other inverter storing "0" to flip the state of the cell. 20,31,32 To measure the WSNM of various SRAM cells at a supply voltage of 0.7 V, we combined the read VTC obtained from the previous subsection with the write VTC. To plot the write VTC (cell is writing "1" into the "0" storing node Q), initially, the cell should be placed in the write mode.…”

Section: Write-abilitymentioning

confidence: 99%

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

Abbasian

Gholipour

Izadinasab

2021

Graphene nanoribbon and transition metal dichalcogenide field-effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal-oxide-semiconductor (MOS) transistor in future technologies. Their competence must be proven through the study and evaluation of various circuits, including static random access memories (SRAMs). Therefore, this paper presents a single-ended 12T (SE12T) SRAM cell designed using GNRFETs and TMDFETs to evaluate their performance. The proposed SE12T cell designed with GNRFETs/TMDFET device improves read static noise margin by 1.95Â/3.20Â and incurs a penalty of 1.16Â/1.14Â in read delay compared to the GNRFETs/TMDFET-based fully differential 8T cell through a read buffer, decoupling the bitline from the storing nodes during the read operation. Furthermore, two transmission gates (TGs) placed inside the cell core cut off the feedback of cross-coupled inverters pair during the write operation, enhancing write static noise margin by 1.65Â/1.71Â. These two TGs along with high logic level of virtual ground (V GND ) control signal during hold mode reduce leakage power. Existence of a higher number of p-type MOS (PMOS) devices, the presence of stacked transistors, and being single-ended bitcell further reduce this metric, nearly 1.48Â/1.17Â designed with GNRFETs/TMDFET device as compared to FD8T. Furthermore, it is observed from the results that GNRFET-based designs have better performance than those of their TMDFET counterparts. The proposed cell eliminates write half-select disturb, and therefore, bit-interleaving architecture can be applied to reduce multi-bit errors.