Double-node-upset aware SRAM bit-cell for aerospace applications

Prasad, Govind; Mandi, Bipin Chandra; Ali, Maifuz

doi:10.1016/j.microrel.2022.114526

Cited by 8 publications

(1 citation statement)

References 37 publications

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“…However, CMOS devices are often subject to collisions with high-energy protons and heavy ions from the cosmic space environment. Therefore, CMOS devices are susceptible to Single Event Effect (SEE) [3][4][5][6]. In particular, Single Event Latch-up (SEL), a special SEE, can alter devices' currents and even cause devices to burn up in severe cases [7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Xin

Zhu

et al. 2023

Electronics

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Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

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Section: Introductionmentioning

confidence: 99%

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Xin

Zhu

et al. 2023

Electronics

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Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Gavaskar¹,

Sivaranjani²,

Elango³

et al. 2022

Wireless Pers Commun

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One of the most critical functions of a computer is memory, as it would be impossible for it to function e ciently without it. The main memory of a computer is known as Random Access Memory (RAM). It stores operating system software, applications, and other data for the central processor unit (CPU) to perform operations swiftly and e ciently. Unfortunately, traditional static RAM (SRAMs) in aerospace applications suffers from high soft error issues such as Single Event Upset (SEU). To overcome the soft error problems, many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD) have been developed, such as 12T We-Quatro, twelve-transistor (12T) Dice SRAM cells, and so on. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 x 32 array architecture. The power consumption of a 32 x 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 x 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology le is used to simulate the comparative analysis for the SRAM cell.

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Design of soft-error resilient SRAM cell with high read and write stability for robust operations

Kumar

Mukherjee

2023

AEU - International Journal of Electronics and Communications

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Double-node-upset aware SRAM bit-cell for aerospace applications

Cited by 8 publications

References 37 publications

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Design of soft-error resilient SRAM cell with high read and write stability for robust operations

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