Design of soft-error resilient SRAM cell with high read and write stability for robust operations

Kumar, Sandeep; Mukherjee, Atin

doi:10.1016/j.aeue.2023.154719

Cited by 8 publications

(5 citation statements)

References 30 publications

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“…We have injected current pulse magnitude of 1.8 mA (equivalent to 50 fC as deposited charge) on each node for SNU and individual node for each DNU pair. As per Kumar and Mukherjee, 4 50 fC charge is large enough for the verification of SNU and DNU resiliencies. Transient pulse width of 100 ps has been considered for the fault simulation.…”

Section: Proposed Dnucr Latchmentioning

confidence: 92%

“…Rather than causing permanent damage to the electronic circuit, such SEU interrupts the operation, corrupts the data, and results in execution errors. Due to the transient nature of an SEU, it is also termed as soft error (SE) 3,4 . Since the latch is the basic sequential element, its ability to resist the SEU has direct impact on robustness of the ICs used in space like radiation‐prone environment.…”

Section: Introductionmentioning

confidence: 99%

“…Using the RHBD approaches, single node upset (SNU) hardened latches such as SEUT, 7 SNUSH, 8 and RH‐1 9 have recently been proposed. However, aggressive scaling of technology node has also raised the concern of multinode upsets (MNU) 1–4,10,11 . In modern IC, the transistors are positioned closer together, and due to the phenomena of charge sharing, a single event's accumulated charge is shared between multiple nodes.…”

Section: Introductionmentioning

confidence: 99%

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Low cost and high performance double‐node upset resilient latch for low orbit space applications

Kumar,

Mukherjee

2023

Circuit Theory & Apps

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SummaryThis paper proposes a double‐node upset complete resilient (DNUCR) latch to meet the requirements of low orbit space applications for high robustness, cost‐effectiveness, and high performance. With the help of its interlocked loops with multiple feedbacks consisting of C‐elements (CE), input splitting CEs, 1P‐2N and 2P‐1N elements, and inverters, the proposed DNUCR latch preserves the original data even after the radiation incident. Error injection simulations in Synopsys HSPICE show that the proposed DNUCR latch recovers from all DNUs and can withstand large amount of injected charge. The simulation outcomes further show that the proposed DNUCR latch outperforms existing DNU‐resilient latches in terms of delay, power consumption, and power–delay–area product (PDAP), with an average of 48% reduction in delay, 22% savings in power, and 60% reduction in PDAP. The proposed DNUCR latch is also found to be the best among the existing radiation‐hardened latches in terms of charge‐to‐PDAP ratio.

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Section: Proposed Dnucr Latchmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low cost and high performance double‐node upset resilient latch for low orbit space applications

Kumar,

Mukherjee

2023

Circuit Theory & Apps

Self Cite

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“…In the TSRAM design of [48] 24 transistors (called 24 T throughout the manuscript) have been utilized to avoid the read disturbance and improvement in SNM and robustness. When the noise gets injected into the cell during its read operation it leads to cell read disturbance which increases the probability of read failure [49][50][51][52]. Though the cell uses separate read and write paths, a ternary sense amplifier is required to sense the trit in this SRAM which increases its power consumption and reduces its stability.…”

Section: Literature Survey On Cntfet-based Tsrammentioning

confidence: 99%

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.

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“…SRAM memory has data persistence, however, it is unstable in the sense that information is absent if the power is off. Synchronous SRAM is quicker than asynchronous SRAM and requires a clock signal to authenticate its control commands, allowing the cache to function in coordination with the central processing unit (CPU) [3,4].…”

Section: Introductionmentioning

confidence: 99%

Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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The purpose of this mechanism is to enhance the chip’s internal connections and read/write memory capabilities. The Advanced Microcontroller Bus Architecture (AMBA) is one such shared bus that uses static random-access memory to achieve this goal. As a result, it’s important to weigh a variety of design options before diving into the Verilog description. It’s also important to remember that the system must be designed to accommodate a large number of interoperable modules and memories. The design, on the other hand, starts with fewer modules and a less complicated description and realisation that relies on memory access. ModelSim is used to simulate after the delay has been modelled in Verilog. Since the interface’s static random-access memory uses an APB protocol, its performance may be tested at this stage. In addition, Questasim employs verification modules and System Verilog technologies to guarantee the system’s operation. From the obtained results, the Direct Memory Access (DMA) with SRAM-APB outperforms the alternatives, particularly in frame transmission schemes, with a wire efficiency that is 1.4 times higher and a dynamic energy efficiency that is nearly twice as high as those of conventional configurations.

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Design of soft-error resilient SRAM cell with high read and write stability for robust operations

Cited by 8 publications

References 30 publications

Low cost and high performance double‐node upset resilient latch for low orbit space applications

Low cost and high performance double‐node upset resilient latch for low orbit space applications

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Development of SRAM-APB protocol interface and verification

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