Process Variation Analysis of 10T SRAM Cell for Low Power, High Speed Cache Memory for IoT Applications

Prasad, Govind; Tandon, Dulari; Isha,; Mandi, Bipin Chandra; Ali, Maifuz

doi:10.1109/spin48934.2020.9070999

Cited by 7 publications

(3 citation statements)

References 14 publications

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“…Low power design has been a significant problem in current portable and small chip designs as complementary metal oxide semiconductor (CMOS) has declined. Speed, power consumption, size, and dependability to enhance performance are the critical areas of concern in today's technology [57].…”

Section: Literature Reviewmentioning

confidence: 99%

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

et al. 2022

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This paper provides an overview of blockchain technology's security and privacy features, as well as an overview of IoT-based cache memory and single-bit six transistor static random-access memory cell sense amplifier architecture. Each chip's memory is used for recorded as blocks, which are encrypted and used as a blockchain for other memory devices. The architectures comprise of the circuit of write driver, six transistor static random access memory cells, and sense amplifiers such as current differential sense amplifier, charge transfer differential sense amplifier, and voltage latch sense amplifier. Furthermore, different parameters such as the number of transistors, sensing delay, and power consumption have been analyzed for varying resistance values (i.e., R=42.3 and R=42.3K ). Apart from that, power reduction techniques such as dual sleep, forced stack, sleep transistor, and sleep stack are used to optimize power consumption. These power reduction techniques are applied over different blocks of architecture, such as six transistors static random access memory cell and sense amplifier to optimize power consumption of the architecture. The conclusion arises that a single-bit six transistor static random access memory cell with power reduction dual sleep technique voltage latch sense amplifier with power reduction dual sleep technique in architecture consumes 11.65µW of power and has 33 transistors which are lowest from other architectures.INDEX TERMS Circuit of write driver (CWD), sense amplifier (SA), current differential sense amplifier (CDSA), charge transfer differential sense amplifier (CTDSA), voltage latch sense amplifier (VLSA), six transistor static random-access memory (6T-SRAM).

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Section: Literature Reviewmentioning

confidence: 99%

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

et al. 2022

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“…PT variations can rapidly affect the sensitivity of the CMOS circuit performance. The process variations are the critical design parameters (die-to-die) in the semiconductor design technology that precisely controls the functionality of the design at the nanometre level [24]. These include film thickness, impurity concentration densities, lateral dimensions and diffusion depths.…”

Section: B Process and Temperature (Pt) Corner Analysismentioning

confidence: 99%

A Comparative Performance Analysis of 6T & 9T SRAM Integrated Circuits: SOI vs. Bulk

Khan¹,

Perdriau²,

Ramdani³

et al. 2022

IEEE Lett. on Electromagn. Compat. Pract. and Appl.

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This paper evaluates the performance of 6T & 9T static random access memory (SRAM) cells, for data stability and power metrics, with the aim to compare silicon-on-insulator (SOI) and bulk CMOS technologies. Each SRAM topology was designed & simulated in 180 nm 5 V XFAB-SOI and AMS-bulk processes, using optimized parameters and compatible devices. The fundamental variables analyzed were read noise margins, write trip current & voltage as well as leakage current (LC) and static power dissipation (SPD) under process and temperature (PT) variations. The static noise margin (SNM) butterfly curve and N-curve methodologies were used to assess the mentioned parameters. Compared to bulk technology, the SRAM cells designed with SOI were found to have lower SPD & LC, higher data stability, lower write ability, larger sensitivity to process variations and higher resilience to temperature deviations.

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“…However, the conventional 6T-SRAM has encountered severe challenges in the implementation of large-capacity memory due to the large cell size (~80 F 2 -120 F 2 ). A memory technology with comparable speed but higher density has been urged by the development of on-chip memory [1][2][3]. In the past fifty years, various new devices have become the driving force for the development of the semiconductor industry.…”

Section: Introductionmentioning

confidence: 99%

A High-Density Memory Design Based on Self-Aligned Tunneling Window for Large-Capacity Memory Application

et al. 2021

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Despite the continuous downscaling of complementary metal–oxide–semiconductor (CMOS) devices, various scenarios of technology have also been proposed toward the shrinking of semiconductor memory. In this paper, a high-density memory (HDM) has been proposed on the basis of band-to-band tunneling (BTBT) for low-power, high density, and high-speed memory applications. The geometric structure and electrical properties have been demonstrated by using TCAD tools. Typical memory operations including read, program, and erase have been designed and performed. High operation speed, lower power consumption, as well as good reliability characteristics have been achieved by simulation, which indicates that the HDM may have potential application value as a novel semiconductor memory device.

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Process Variation Analysis of 10T SRAM Cell for Low Power, High Speed Cache Memory for IoT Applications

Cited by 7 publications

References 14 publications

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

A Comparative Performance Analysis of 6T & 9T SRAM Integrated Circuits: SOI vs. Bulk

A High-Density Memory Design Based on Self-Aligned Tunneling Window for Large-Capacity Memory Application

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