In this paper we investigate the physical and electrical properties of silicon layers grown by molecular beam epitaxy on 4H-SiC substrates, evaluating the effect of the Si doping, Si temperature deposition, and SiC surface cleaning procedure. Si∕SiC monolithic integration of Si circuits with SiC power devices can be considered as an attractive proposition and has the potential to be applied to a broad range of applications. X-ray diffraction and scanning electron microscopy are used to determine the Si crystal structure (cubic silicon) and morphology. I-V and C-V measurements are performed to evaluate the rectifying diode characteristics along with the Si∕SiC built-in potential and energy band offsets. In the last section, we propose that our Si∕SiC heteojunction diode current characteristics can be explained by an isojunction drift-diffusion and thermoionic emission model where the effect of doping concentration of the silicon layer and its conduction band offset with SiC is analyzed.

This paper describes the thermal oxidation of Si/SiC heterojunction structures, produced using a layer-transfer process, as an alternative solution to fabricating SiC metal-oxide-semiconductor ͑MOS͒ devices with lower interface state densities ͑D it ͒. Physical characterization demonstrate that the transferred Si layer is relatively smooth, uniform, and essentially monocrystalline. The Si on SiC has been totally or partially thermally oxidized at 900-1150°C. D it for both partially and completely oxidized silicon layers on SiC were significantly lower than D it values for MOS capacitors fabricated via conventional thermal oxidation of SiC. The quality of the SiO 2 , formed by oxidation of a wafer-bonded silicon layer reported here has the potential to realize a number of innovative heterojunction concepts and devices, including the fabrication of high quality and reliable SiO 2 gate oxides.

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In this article, we report on the physical and electrical nature of Ge/SiC heterojunction layers that have been formed by MBE deposition. Using X-ray diffraction, atomic force microscopy and helium ion microscopy, we perform a thorough analysis of how MBE growth conditions affect the Ge layers. We observe the layers developing from independent islands at thicknesses of 100 nm to flat surfaces at 300 nm. The crystallinity and surface quality of the layer is shown to be affected by the deposition parameters and, using a high temperature deposition and a light dopant species, the layers produced have large polycrystals and hence a low resistance. The p-type and n-type layers, 300 nm thick are formed into Ge/SiC heterojunction mesa diodes and these are characterised electrically. The polycrystalline diodes display near ideal diode characteristics (n < 1.05), low on resistance and good reverse characteristics. Current-voltage measurements at varying temperature prove that all the layers have two-dimensional fluctuations in the Schottky barrier height (SBH) due to inhomogeneities at the heterojunction interface. Capacitance-voltage analysis and the SBH size extracted from I-V analysis suggest strongly that interface states are present at the surface causing Fermi-level pinning throughout the bands. A simple model is used to quantify the concentration of interface states at the surface.

In this paper we investigate the physical and electrical properties of germanium deposited on 4H silicon carbide substrates by molecular beam epitaxy. Layers of highly doped and intrinsic germanium were deposited at 300 and 500 °C and compared. Current-voltage measurements reveal low turn-on voltages. The intrinsic samples display ideality factors of 1.1 and a reverse leakage current of 9×10−9 A/cm2, suggesting a high quality electrical interface. X-ray diffraction analysis reveals the polycrystalline nature of the high-temperature depositions, whereas the low-temperature depositions are amorphous. Atomic force microscopy shows that the low-temperature layers have a rms roughness of 3 nm.

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