2007
DOI: 10.1063/1.2752148
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Characterization and modeling of n-n Si∕SiC heterojunction diodes

Abstract: In this paper we investigate the physical and electrical properties of silicon layers grown by molecular beam epitaxy on 4H-SiC substrates, evaluating the effect of the Si doping, Si temperature deposition, and SiC surface cleaning procedure. Si∕SiC monolithic integration of Si circuits with SiC power devices can be considered as an attractive proposition and has the potential to be applied to a broad range of applications. X-ray diffraction and scanning electron microscopy are used to determine the Si crystal… Show more

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Cited by 59 publications
(41 citation statements)
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“…The SAED patterns of the p/n-Si DSL corresponding to Si[011] zone axes are shown in Fig. 2(b), confirming the epitaxial growth of the Si films with [1][2][3][4][5][6][7][8][9][10][11] preferred orientation. Figure 2(c) shows a highresolution TEM image of the p-Si/n-Si interface.…”
Section: Resultsmentioning
confidence: 51%
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“…The SAED patterns of the p/n-Si DSL corresponding to Si[011] zone axes are shown in Fig. 2(b), confirming the epitaxial growth of the Si films with [1][2][3][4][5][6][7][8][9][10][11] preferred orientation. Figure 2(c) shows a highresolution TEM image of the p-Si/n-Si interface.…”
Section: Resultsmentioning
confidence: 51%
“…The electrons are the dominated current carriers because of the low electron barrier. TEM characterizations of the p/n-Si DSL confirms the epitaxial growth of the Si films with [1][2][3][4][5][6][7][8][9][10][11] preferred orientation and the misfit dislocations with a Burgers vector of 1/3 <21-1˃ at the pSi/n-Si interface. Under visible illumination with light intensity of 0.6W/cm 2 , the heterostructure demonstrates significant photoelectric response, and the photocurrent density is 2.1mA/cm2 Non-UV operation of the SiCbased photoelectric device is realized.…”
Section: Resultsmentioning
confidence: 87%
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“…As mentioned above, CVD, MBE, or EBE-UHV of Si on to SiC results in polycrystalline or amorphous Si layers. The large lattice mismatch induces Stranski-Krastanow growth or polycrystalline island formation during the growth process, 8 which is a major impediment when considering the oxidation of the Si layer due to a poor aspect ratio. In contrast XRD scans of the wafer-bonded Si layer reveal only a single cubic silicon phase, c-Si ͗400͘, which corresponds to the same crystalline phase as that in the donor Si wafer.…”
mentioning
confidence: 99%
“…We have previously reported investigations using several techniques to grow Si on SiC including the following: chemical vapor deposition ͑CVD͒, molecular beam epitaxy ͑MBE͒, and electron beam evaporation under UHV conditions ͑EBE-UHV͒. 6,8,9 However, the large lattice mismatch between Si and SiC prevented each of the aforementioned techniques from achieving a Si layer with sufficient quality for a MOS gated device. In 2008, 10 we reported the successful layer transfer ͑LT͒ of a thin silicon layer, suitable for MOS device fabrication, onto a 3 in.…”
mentioning
confidence: 99%