Germanium possesses higher electron and hole mobilities than silicon. There is a big leap, however, between these basic material parameters and implementation for high-performance microelectronics. Here we discuss some of the major issues for Ge metal oxide semiconductor field effect transistors ͑MOSFETs͒. Substrate options are overviewed. A dislocation reduction anneal Ͼ800°C decreases threading dislocation densities for Ge-on-Si wafers 10-fold to 10 7 cm −2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at ϳ6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for pϩ/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H 2 anneal for device performance is shown.

We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a Wbased SOT underlayer have very large endurance (> 5x10 10 ), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.Introduction: The introduction of non-volatility (NV) at the cache level in advance logic nodes is sought as it would lead to a large decrease of the power consumption of microprocessors. Among NV memory technologies, spin-transfer torque (STT) MRAM has gained a lot of attention due to its scalability, low power and high speed, as well as compatibility with scaled CMOS processes and voltages. Despite all these advantages, STT-MRAM cannot operate reliably at ns and sub-ns scales due to large incubation delays [1,2], making it an unsuitable solution to tackle L1/2 SRAM cache replacement. In addition, the shared read/write path can impair the read reliability, while the write current can impose severe stress on the MTJ, leading to time dependent degradation of the memory cell. To mitigate these issues, spin-orbit torque (SOT)-MRAM has been recently proposed [2,3]. SOT induces switching of the free layer (FL) of the MTJ by injecting an in-plane current in an adjacent SOT layer, typically with the assistance of a static in-plane magnetic field [2]. This enables a three terminal MTJ-based concept that isolates the read/write path (Fig. 1), significantly improving the device endurance and read stability. Moreover, due to SOT spin transfer geometry, incubation time is negligible which allows for reliable switching operation at sub-ns timescales [4,5]. Here, we report the first successful integration of SOT-MTJ cells on 300 mm wafers using CMOS-compatible processes. We demonstrate low power sub-ns switching and pathways for further optimization. Finally, excellent endurance and absence of electro-migration effect of ultrathin SOT layers are shown.Integration flow: We used a SOT dedicated mask set in the imec 300 mm fab. The main steps of the integration process are summarized in Fig. 2: a SOT-MTJ stack is deposited on smooth bottom electrodes (BE), which are fabricated using a tungsten (W) damascene process. The MTJ is top pinned and consist of SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized (PMA) stack, where the SOT layer is W-based. Specific stop etch conditions have been developed to leave the SOT layer intact while patterning the MTJ pillar without producing sidewall shorts across the MgO barrier (Fig. 2c,d). Subsequently, the SOT layer is etched to form the three terminal device and a dual damascene Cu top electrode (TE) was fabricated to complete the electrical connection ( Fig. 2a).Stack development: SOTs possess a damping-like term (τDL) attributed to spin Hall and a field-like term (τFL) attributed to interface interactions [2]. Recent work indicates that τDL triggers switching while τFL accelerates it [5]. Charge-to-spin conversion efficiency parameters θDL and...

Strain relaxation in large lattice-mismatched epitaxial films, such as Ge and III-V materials on Si, introduces high threading dislocation densities ͑TDDs͒. A thermodynamic model of TDD dependence on film thickness is developed. According to this model, the quasiequilibrium TDD of a given strain-relaxed film scales down with the inverse square of its thickness. The quasiequilibrium TDDs in both Ge and GaAs films follow this model consistently. Our model predicts the lowest possible TDD of a large lattice-mismatched film on Si ͑100͒, which is determined by the dislocation glide activation energy and the film thickness.

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Further improving complementary metal oxide semiconductor performance beyond the 22 nm generation likely requires the use of high mobility channel materials, such as Ge for p-type metal oxide semiconductor (pMOS) and III/V for n-type metal oxide semiconductor devices. The complementary integration of both materials on Si substrates can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates using Si wafers with standard shallow trench isolation (STI). This reduces the fabrication cost of these virtual substrates as the complicated isolation scheme in blanket Ge can be omitted. The low topography enables integration of ultrathin high- k gate dielectrics. The fabrication schemes are also compatible with uniaxial stress techniques. Both modules include an annealing step at 850°C to reduce the threading dislocation densities down to 4×108 and 1×107cm−2 , respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter are illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates.

We are concerned herein with inverse scattering problems in stratified media and aspect-limited data configurations. In such configurations, the sources and receivers of the probing waves are located in a medium different from the one which contains the object under test. This results in a lack of information which enhances the inherent ill-posedness of the inverse problem. To make the problem more tractable, we assume that the test object is homogeneous with known constitutive parameters so that the inverse problem consists of reconstructing its shape and location. This non-linear inverse problem is solved using the modified gradient method in which the a priori information is introduced as a binary constraint. A cooling parameter is introduced at the same time, which allows us to control the evolution of the iterative process. The effectiveness of this algorithm is studied for three different physical applications.

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