Capacitor-less, Long-Retention (&gt;400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM

Belmonte, Attilio; Oh, H.; Rassoul, Nouredine; Donadio, Gabriele Luca; Mitard, J.; Dekkers, Harold; Delhougne, Romain; Subhechha, Subhali; Chasin, Adrian; Setten, Michiel J. van; Ključar, Luka; Mao, Ming; Puliyalil, Harinarayanan; Pak, M.; Teugels, Lieve; Tsvetanova, Diana; Banerjee, K.; Souriau, Laurent; Tőkei, Zs.; Goux, L.; Kar, Gouri Sankar

doi:10.1109/iedm13553.2020.9371900

Cited by 87 publications

(59 citation statements)

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“…To further explore the performance of spinel IGZO devices and their potential use for stacking-compatible capacitor-less DRAM cells with >400 s retention time, 40 a similar device structure was built in a front-gated configuration (Figure 9b). Now a 7 nm SiO 2 serves as a front gate dielectric, with a TiN/ W stack acting as gate metal terminal.…”

Section: ■ Morphologymentioning

confidence: 99%

Deposition, Characterization, and Performance of Spinel InGaZnO₄

Dekkers

Setten

Belmonte

et al. 2022

ACS Appl. Electron. Mater.

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Polycrystalline indium−gallium−zinc oxide (IGZO) in the spinel phase was obtained by physical vapor deposition (PVD), using reactive sputtering from an IGZO target with In/Ga/ Zn = 1:1:1 composition. The initial growth of spinel IGZO is investigated by X-ray diffraction measurements after annealing the film. Deposition of spinel IGZO initially starts as a mixed amorphous/c-axis-aligned crystalline (CAAC) film, after which a metastable spinel IGZO is formed. Using a template of polycrystalline spinel Ga 2 ZnO 4 , the growth of the spinel phase is immediately achieved and enables the electrical characterization of pure spinel IGZO channels in scaled thin-film field-effect transistors. The average effective channel field-effect mobility of spinel IGZO of 50 ± 10 cm 2 /(V s) is slightly higher than amorphous IGZO in the same devices. This is in line with a slightly lower effective electron mass, as is calculated with density functional theory. The calculated total energies and band gaps have similar values to CAAC-IGZO. This metastable nature identifies spinel IGZO as an intermediate phase before the onset of CAAC-IGZO formation during PVD. Spinel IGZO is an interesting alternative to amorphous IGZO (a-IGZO) and CAAC-IGZO because of potentially higher robustness to oxygen vacancy formation.

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Section: ■ Morphologymentioning

confidence: 99%

Deposition, Characterization, and Performance of Spinel InGaZnO₄

Dekkers

Setten

Belmonte

et al. 2022

ACS Appl. Electron. Mater.

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“…3D integration of DRAM bitcell to improve the performance is an essential requirement for the performance of large scale machine learning workloads. The scalability is severely limited by the requirement of bitcell storage capacitor [17]. Thus, the capacitorless IGZO based eDRAM alleviates this problem by utilizing the gate capacitance of the read port transistor as the storage capacitor.…”

Section: Bitcell Studymentioning

confidence: 99%

“…The capacitorless IGZO based eDRAM can offer higher array density benefits as opposed to the 3T1C eDRAM based bitcell because of 3D stacking without loss in storage density, thus making it opportune for high performance, high density CIM designs.IGZO eDRAM bitcells with dedicated read port have been explored before [1]. However, prior approaches [13] [14] consider only 1 bit/cell CIM design. However, this work explores the possibility of MLC in IGZO eDRAM and efficiently mapping ternary weights in a neural network for CIM applications considering device-circuit-architecture level analysis.…”

Section: Introductionmentioning

confidence: 99%

IGZO CIM: Enabling In-Memory Computations Using Multilevel Capacitorless Indium–Gallium–Zinc–Oxide-Based Embedded DRAM Technology

Raman

Xie

Kulkarni

2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Compute in memory(CIM) is a promising approach for efficiently performing data-centric computing (such as neural network computations). Among the multiple semiconductor memory technologies, embedded DRAM (eDRAM), which integrates the DRAM bitcell with high performance logic transistors can enable efficient CIM designs. However, Silicon based eDRAM technology suffers from poor retention time incurring significant refresh power overhead. However, eDRAM using back end of the line integrated C-axis aligned crystalline (CAAC) Indium Gallium Zinc Oxide transistors (IGZO), exhibiting extreme low leakage is promising memory technology with lower refresh power overhead. Long retention time in IGZO eDRAM can enable multi-level cell functionality which can improve its efficacy in CIM applications. In this article, we explore capacitorless IGZO eDRAM based multi-level cell, capable of storing 1.5bits/cell for CIM designs focussed on DNN inference applications. We perform a detailed design space exploration of IGZO eDRAM sensitivity to process, temperature variations for read, write and retention operations followed by architecture level simulations comparing performance and energy for different workloads. The effectiveness of IGZO eDRAM based CIM architecture is evaluated using a representative neural network and the proposed approach achieves 82% Top-1 inference accuracy for the CIFAR-10 dataset, compared to 87% software accuracy with high bitcell storage density.

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“…Amorphous InGaZnO (a-IGZO) is a promising channel material due to its low processing temperature, low leakage current, high uniformity, and high mobility. IGZO TFTs enable various applications such as large-size active matrix displays [1], monolithic 3D stacking [2], backend of line (BEOL) transistors [3], dynamic random access memory (DRAM) [4], and neuromorphic computations [5].…”

Section: Introductionmentioning

confidence: 99%