A model of threading dislocation density in strain-relaxed Ge and GaAs epitaxial films on Si (100)

Wang, G.; Loo, Roger; Simoen, Eddy; Souriau, Laurent; Caymax, Matty; Heyns, Marc; Blanpain, Bart

doi:10.1063/1.3097245

Cited by 95 publications

(93 citation statements)

References 22 publications

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“…4(b). The density tends to be reduced with increasing the layer thickness [19], while a post-growth annealing at high temperatures (800-900°C) [18] is effective to reduce the threading dislocation density below 10 8 cm −2 , as in the bottom of Fig. 4(b) and in Fig.…”

Section: Epitaxial Growth Of Ge On Simentioning

confidence: 93%

Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Ishikawa

Saito

2014

IEICE Electron. Express

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Section: Epitaxial Growth Of Ge On Simentioning

confidence: 93%

Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Ishikawa

Saito

2014

IEICE Electron. Express

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“…Overall, it is concluded that below a TDD of 10 7 cm −2 , no further reduction in the junction leakage current density is observed for p + n diodes compatible with the source and drain of Ge CMOS. 8 In addition, although it is advantageous to grow thicker Ge layers, as this reduces the TDD, [9][10][11] for the selective Ge epitaxial growth in shallow trench isolation ͑STI͒ wafers, the thickness of the layer is set approximately by the STI depth so that PG annealing is crucial in improving the layer quality [12][13][14][15] and the device performance. 8,16,17 It is pointed out, finally, that for thin Ge-on-Si layers, the presence of the Ge-Si heterojunction and the associated misfit defects may affect the electrical characteristics ͑leakage current and capacitance vs voltage͒ at a sufficiently large reverse bias V R .…”

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confidence: 99%

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Simoen

Eneman

Wang

et al. 2010

J. Electrochem. Soc.

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Extended-defect aspects of state-of-the-art Ge-on-Si materials and devices are discussed with an emphasis on the impact of postgrowth thermal budget on the structural and electrical epilayer characteristics. The observations on the annealed thick and thin epitaxial layers on Si can be explained based on a thermodynamic model for the minimum density of threading dislocations ͑TDs͒. For the present processing conditions, the leakage current of Ge complementary metal oxide semiconductor compatible p + n junctions becomes independent of the TD density at about 10 7 cm −2 . © 2009 The Electrochemical Society. ͓DOI: 10.1149/1.3267514͔ All rights reserved. Defect engineering is a common practice in silicon-based integrated circuit and solar cell technology and has been extensively investigated during the past 2 decades, leading to its successful implementation in manufacturing lines. In addition, for sub-45 nm technologies, strain engineering is required to boost the device performance in agreement with the International Technology Roadmap for Semiconductors. In recent years, strong research efforts have also been focusing on the use of Ge-based channels for the sub-22 nm complementary metal oxide semiconductor ͑CMOS͒ node, 1 whereby epitaxial Ge-on-Si has a very strong potential. This also opens the door to achieve a full monolithic integration of Ge and III-V materials on a silicon substrate, leading to system-on-chip applications. The main challenge of the epitaxial deposition of Ge on Si is the 4% lattice mismatch and the difference in thermal expansion coefficient, which readily leads to the buildup of mechanical stress and, subsequently, its relaxation by the generation of misfit and threading dislocations ͑TDs͒.2,3 Therefore, the control of misfit and TDs during both substrate preparation and device processing is a must to arrive at a good-yielding, high performing technology. The aim of this paper is to summarize our recent developments in Geon-Si materials and devices and to address the remaining challenges. An extensive overview of the foregoing work can be found in Chap. 4 of Ref. 4.The focus in this work is on the defect formation and control during the fabrication of Ge virtual substrates on silicon by chemical vapor deposition. Hereby, several approaches can be followed 2-4 to optimize the threading dislocation density ͑TDD͒ either by the use of a relaxed SiGe-graded buffer layer or by the direct deposition of a thick Ge epitaxial layer on silicon. Three different cases are considered, whereby the impact of a postgrowth ͑PG͒ anneal on the TDD is highlighted, and the impact on the electrical device performance is mainly evaluated through the leakage current of p + n junctions fabricated in these layers. The procedures to separate the area from the perimeter leakage current have been outlined previously. 5,6 It is demonstrated that a PG anneal or thermal budget may have both beneficial and detrimental effects, depending on the application and type of layer. For a relaxed virtual Ge substrate, the PG anneali...

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“…During the GaAs epitaxial growth procedure, some stacking faults for GaAs on Si multiply or self-annihilate. A previous report indicated that a threading dislocation density of above 10 7 cm −2 for a 900 nm-thick epilayer decreased to 10 6 cm −2 when the film thickness was increased to above 4 µm [21]. In this study, the use of a RNS Si(001) substrate with an aspect ratio of 4.7 effectively reduced the number of thin-film dislocations for small epilayer thicknesses (<1 µm).…”

Section: Resultsmentioning

confidence: 69%

Nanoepitaxy of GaAs on a Si(001) substrate using a round-hole nanopatterned SiO₂mask

Hsu

Chen

2012

Nanotechnology

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GaAs is grown by metal-organic vapor-phase epitaxy on a 55 nm round-hole patterned Si substrate with SiO2 as a mask. The threading dislocations, which are stacked on the lowest energy facet plane, move along the SiO2 walls, reducing the number of dislocations. The etching pit density of GaAs on the 55 nm round-hole patterned Si substrate is about 3.3 × 105 cm−2. Compared with the full width at half maximum measurement from x-ray diffraction and photoluminescence spectra of GaAs on a planar Si(001) substrate, those of GaAs on the 55 nm round-hole patterned Si substrate are reduced by 39.6 and 31.4%, respectively. The improvement in material quality is verified by transmission electron microscopy, field-emission scanning electron microscopy, Hall measurements, Raman spectroscopy, photoluminescence, and x-ray diffraction studies.

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A model of threading dislocation density in strain-relaxed Ge and GaAs epitaxial films on Si (100)

Cited by 95 publications

References 22 publications

Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Nanoepitaxy of GaAs on a Si(001) substrate using a round-hole nanopatterned SiO₂mask

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A model of threading dislocation density in strain-relaxed Ge and GaAs epitaxial films on Si (100)

Cited by 95 publications

References 22 publications

Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Nanoepitaxy of GaAs on a Si(001) substrate using a round-hole nanopatterned SiO2mask

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Nanoepitaxy of GaAs on a Si(001) substrate using a round-hole nanopatterned SiO₂mask