High Quality Ge Virtual Substrates on Si Wafers with Standard STI Patterning

Loo, Roger; Wang, G.; Souriau, Laurent; Lin, Jason; Takeuchi, Shinichi; Brammertz, Guy; Caymax, Matty

doi:10.1149/1.3244564

Cited by 107 publications

(90 citation statements)

References 36 publications

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“…The trench formation is described in more detail in Refs. [6,16]. The result is that our starting STI wafers have 300 nm thick embedded SiO2 and, by selective etch of Si with HCI vapor, trenches are formed.…”

Section: Methodsmentioning

confidence: 98%

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Growth of high quality InP layers in STI trenches on miscut Si (001) substrates

Wang

Leys

Nguyen

et al. 2011

Journal of Crystal Growth

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In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 61 miscut toward (1 1 1) using a thin Ge buffer layer. We studied the impact of growth rates and steric hindrance effects on the nano-twin formation at the STI side walls. It was found that a too high growth rate induces more nano-twins in the layer and results in InP crystal distortion. The STI side wall tapering angle and the substrate miscut angle induced streric hindrance between the InP facets and the STI side walls also contribute to defect formation. In the [ 1 0] orientated trenches, when the STI side wall tapering angle is larger than 10°, crystal distortion was observed while the substrate miscut angle has no significant impact on the InP defect formation. In the [ 1 0] trenches, both the increased STI tapering angle and the substrate miscut angle induce high density of defects. With a small STI tapering angle and a thin Ge layer, we obtained extended defect free InP in the top region of the [1 1 0] trenches with aspect ratio larger than 2.

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Section: Methodsmentioning

confidence: 98%

“…About 40% of the total Si wafer surface was exposed for the InP deposition. In an ASM-Epsilon 2000 reactor [16], following the Si etch, a thin (40 nm) Ge layer was grown at 450 °C and atmospheric pressure using GeH4 (1% in H2) in H2 carrier gas. From Ref.…”

Section: Methodsmentioning

confidence: 99%

Growth of high quality InP layers in STI trenches on miscut Si (001) substrates

Wang

Leys

Nguyen

et al. 2011

Journal of Crystal Growth

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“…As mentioned above the new high-mobility channel materials can be integrated on silicon carrier wafers inside narrow trenches using selective epitaxial growth [5] as schematically depicted in Figure 6. Narrow trenches in SiO 2 on silicon wafers are made using Shallow Trench Isolation (STI) patterning technologies.…”

Section: Post-cmp and Pre-epi Cleaning Of Sige And Iii-v Buffer Layermentioning

confidence: 99%

“…The exposure of SiGe to APM should therefore be restricted to short times and very dilute composition such as 1/1/5000. [5] 2 w-% HF <0.090 <0.099 <0.11 [5] 1 M HNO 3 --0.14±0.013 [6] 96 w-% H 2 SO 4 --0.16±0.006 [6] H 2 O <0.022 <0.049 <0.036 [5] H 2 O (O 2 -bubbling) --0.005 [6] DIW-O 3 (1 w-ppm) 0.15±0.23 0.24±0.28 1.1±0.1 [5] pH 11 NH 4 OH (1:100) --0.29±0.007 [6] '-' : not measured In order to evaluate different cleaning processes on their capability of removing surface oxides, Si 45 Ge 55 layers where oxidized in a dry UV O 3 furnace at room temperature. Concentrated HCl does not noticibly remove any of the oxides.…”

Section: Post-cmp and Pre-epi Cleaning Of Sige And Iii-v Buffer Layermentioning

confidence: 99%

Cleaning Challenges and Solutions for Advanced Technology Nodes

Mertens¹,

Vos²,

Wada³

et al. 2011

ECS Trans.

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Trends in further scaled CMOS technologies are reviewed with respect to the implications for cleaning and wet processing. Particularly the FEOL processes are being considered such as selective cap removal, pre-epi cleaning and post I/I photo resist removal. For technologies beyond the 15nm, several aspects of wet processing of potential new materials, such as Ge and III-V, and advanced integration schemes are covered.

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“…GERMANIUM-ON-SILICON PLATFORM Epitaxial Ge, 1 and 2 µm thick was grown on an n-type Si(001) substrate at imec on 200mm wafers by an atmospheric chemical vapor deposition system as described in [6]. Since there is a lattice mismatch of 4.2% between Si and Ge, the threading dislocation density(TDD) is quite high at the Si-Ge interface.…”

Section: Introductionmentioning

confidence: 99%

Germanium-on-silicon mid-infrared waveguides and Mach-Zehnder interferometers

Malik

Muneeb

Shimura

et al. 2013

2013 IEEE Photonics Conference

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Abstract-In this paper we describe Ge-on-Si waveguides and Mach-Zehnder interferometers operating in the 5.2 -5.4 µm wavelength range. 3dB/cm waveguide losses and Mach-Zehnder interferometers with 20dB extinction ratio are presented. Index Terms-mid-infrared, photonic integrated circuits, germanium on silicon I. INTRODUCTIONThe mid-infrared wavelength range is a region of interest for spectroscopic sensing applications, due to strong and specific absorption features of many molecules in that wavelength range [1]. This allows for a non-contact method to detect the presence and concentration of these molecules. Quantum cascade lasers and inter-band cascade lasers are used as coherent laser sources in this wavelength range. These are typically single-wavelength lasers with limited tuning range. Other options are the use of broadband incoherent thermal sources or coherent supercontinuum sources in combination with a spectrometer. Current instrumentation is bulky, expensive and power hungry, necessitating the need for a midinfrared photonic integration platform to mitigate these disadvantages. Several functions can be implemented on such a platform, such as wavelength multiplexers for arrays of single wavelength QCL lasers allowing to cover a broad wavelength range and the integration of spectrometers for spectral analysis of broadband sources after they passed through a gas or liquid under study. For telecom wavelengths, Silicon-on-Insulator (SOI) is now a standard waveguide platform. One of the main reasons for this is the compatibility with CMOS fabrication technology and the associated potential for large volume manufacturing at low cost. However, beyond 3.8 µm, the underlying buried oxide layer starts absorbing heavily [2]. There are several candidates for viable waveguide platforms for the mid-IR wavelength range beyond 3.8 µm as discussed primarily in [2]. There have been reports in recent literature on Ge-on-Si waveguides [3], free-standing Si waveguides [4] and silicon-on-sapphire waveguides [5]. In this paper we describe the fabrication of Ge-on-Si photonic integrated circuits, an attractive option for mid-IR photonics and present waveguide losses and a key photonic component in wavelength multiplexers and spectrometers: the Mach-Zehnder Interferometer (MZI).

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High Quality Ge Virtual Substrates on Si Wafers with Standard STI Patterning

Cited by 107 publications

References 36 publications

Growth of high quality InP layers in STI trenches on miscut Si (001) substrates

Growth of high quality InP layers in STI trenches on miscut Si (001) substrates

Cleaning Challenges and Solutions for Advanced Technology Nodes

Germanium-on-silicon mid-infrared waveguides and Mach-Zehnder interferometers

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