a Metallic nanowire networks have huge potential in devices requiring transparent electrodes. This article describes how the electrical resistance of metal nanowire networks evolve under thermal annealing.Understanding the behavior of such films is crucial for the optimization of transparent electrodes which find many applications. An in-depth investigation of silver nanowire networks under different annealing conditions provides a case study demonstrating that several mechanisms, namely local sintering and desorption of organic residues, are responsible for the reduction of the systems electrical resistance. Optimization of the annealing led to specimens with transmittance of 90% (at 550 nm) and sheet resistance of 9.5 Ω sq −1. Quantized steps in resistance were observed and a model is proposed which provides good agreement with the experimental results. In terms of thermal behavior, we demonstrate that there is a maximum thermal budget that these electrodes can tolerate due to spheroidization of the nanowires. This budget is determined by two main factors: the thermal loading and the wire diameter. This result enables the fabrication and optimization of transparent metal nanowire electrodes for solar cells, organic electronics and flexible displays.

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation ͑STI͒ structures on Si͑001͒ substrates 6°off-cut toward ͑111͒. Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO 2 . However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in ͓110͔ trenches. High quality InP layers were obtained in the top of the trenches along ͓110͔. The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2.

Transparent electrodes (TEs) are pivotal components in many modern devices such as solar cells, light‐emitting diodes, touch screens, wearable electronic devices, smart windows, and transparent heaters. Recently, the high demand for flexibility and low cost in TEs requires a new class of transparent conductive materials (TCMs), serving as substitutes for the conventional indium tin oxide (ITO). So far, ITO has been the most used TCM despite its brittleness and high cost. Among the different emerging alternative materials to ITO, metallic nanomaterials have received much interest due to their remarkable optical‐electrical properties, low cost, ease of manufacturing, flexibility, and widespread applicability. These involve metal grids, thin oxide/metal/oxide multilayers, metal nanowire percolating networks, or nanocomposites based on metallic nanostructures. In this review, a comparison between TCMs based on metallic nanomaterials and other TCM technologies is discussed. Next, the different types of metal‐based TCMs developed so far and the fabrication technologies used are presented. Then, the challenges that these TCMs face toward integration in functional devices are discussed. Finally, the various fields in which metal‐based TCMs have been successfully applied, as well as emerging and potential applications, are summarized.

Advancement in the science and technology of random metallic nanowire (MNW) networks is crucial for their appropriate integration in many applications including transparent electrodes for optoelectronics and transparent film heaters. We have recently highlighted the discontinuous activation of efficient percolating pathways (EPPs) for networks having densities slightly above the percolation threshold. Such networks exhibit abrupt drops of electrical resistance when thermal or electrical annealing is performed, which gives rise to a "geometrically quantized percolation". In this Letter, lock-in thermography (LiT) is used to provide visual evidence of geometrical quantized percolation: when low voltage is applied to the network, individual "illuminated pathways" can be detected, and new branches get highlighted as the voltage is incrementally increased. This experimental approach has allowed us to validate our original model and map the electrical and thermal distributions in silver nanowire (AgNW) networks. We also study the effects of electrode morphology and wire dimensions on quantized percolation. Furthermore, we demonstrate that the network failure at high temperature can also be governed by a quantized increase of the electrical resistance, which corresponds to the discontinuous destruction of individual pathways (antipercolation). More generally, we demonstrate that LiT is a promising tool for the detection of conductive subclusters as well as hot spots in AgNW networks.

An original self-powered UV photodetector integrating ZnO/CuCrO 2 core-shell nanowire heterostructures is fabricated using low-cost and scalable chemical deposition techniques operating at moderate temperatures. A 35 nm thick delafossite phase CuCrO 2 shell is formed with high uniformity by aerosol-assisted chemical vapor deposition over an array of vertically aligned ZnO nanowires grown by chemical bath deposition. The CuCrO 2 shell consists of columnar grains at the top of ZnO nanowires as well as nanograins with some preferential orientations on their vertical sidewalls. The ZnO/CuCrO 2 core-shell nanowire heterostructures exhibit significant diode behavior, with a rectification ratio approaching 1.2 × 10 4 at 1 V and -1 V, as well as a high optical absorptance above 85% in the UV part of the electromagnetic spectrum. A high UV responsivity at zero bias under low-power illumination of up to 3.43 mA W -1 under a 365 nm UV lamp, and up to 5.87 mA W -1 at 395 nm from spectrally resolved measurements, alongside a high selectivity with a UV-to-visible (395-550 nm) rejection ratio of 106 is measured. The short rise and decay times of 32 and 35 µs, respectively, both measured at zero bias, further establish these devices as promising candidates for cost-efficient, all-oxide self-powered UV photodetectors.

We present the epitaxial growth of Ge and Ge 0.94 Sn 0.06 layers with 1.4% and 0.4% tensile strain, respectively, by reduced pressure chemical vapor deposition on relaxed GeSn buffers and the formation of high-k/metal gate stacks thereon. Annealing experiments reveal that process temperatures are limited to 350 °C to avoid Sn diffusion. Particular emphasis is placed on the electrical characterization of various high-k dielectrics, as 5 nm Al 2 O 3 , 5 nm HfO 2 , or 1 nmAl 2 O 3 /4 nm HfO 2 , on strained Ge and strained Ge 0.94 Sn 0.06 . Experimental capacitance− voltage characteristics are presented and the effect of the small bandgap, like strong response of minority carriers at applied field, are discussed via simulations.

Hole mobility in N , NЈ-diphenyl-N , NЈ-bis͑1-naphtylphenyl͒-1,1Ј-biphenyl-4 , 4Ј-diamine ͑␣-NPD͒ is evaluated by electrical characterization in the ac regime. The frequency-dependent complex admittance and impedance of the structure consisting of the organic layer, grown by thermal evaporation, sandwiched by indium tin oxide and aluminum electrodes, are measured as functions of the applied dc voltage. The capacitance response shows negative values for frequencies below a characteristic value depending on the bias and ranging from 0.1 Hz up to 20 Hz. It increases with the modulation frequency and reaches a peak, the magnitude and position of which are functions of the applied voltage. For higher frequencies, a minimum can be observed before the capacitance increases again up to a constant value. A final decreasing occurs at frequency of 4 ϫ 10 6 Hz. The analysis of the experimental data is performed by a detailed theoretical study of the steady-state and smallsignal electrical characteristics of the device. Numerical calculations are based on the solution of the basic semiconductor equations for the system consisting of two electrodes connected by the semiconducting channel formed by the organic layer. The description explicitly includes a continuous distribution of trap density of states and a field-dependent carrier mobility. The spatially dependent charge carrier and occupied trap concentrations, as well as the various components to the total current density, are obtained for the dc and ac regimes and are analyzed for given bias and frequency. Based on a formalism used in the study of inorganic semiconductors, the results of the simulation show that the inductive contribution to the capacitance response originates from the modulation of the hole concentration in the organic material, leading to the corresponding carrier transit time. Moreover, the low-frequency behavior of the capacitance curves could be explained by the presence of a band of defect states which modifies the charge distribution within the organic layer and the injection of electrons from the cathode. We show that the latter contribution is also responsible for the negative values of the capacitance measured below 10 Hz. Good agreement is observed between the experimental and theoretical electrical characteristics, in particular for the differential susceptance results and the subsequent hole mobility values. Our approach can be a useful contribution for the methodology of obtaining mobilities from admittance measurements as it allows one to clarify the physical origin of the measured frequencydependent capacitance and to check for the experimental procedure. This work finally leads to the formulation of the conditions under which small-signal ac measurements can be used to determine carrier mobility in organic devices.

This paper provides an overview of the physical vapor technologies used to synthesize Cu 2 ZnSn(S,Se) 4 thin films as absorber layers for photovoltaic applications. Through the years, CZT(S,Se) thin films have been fabricated using sequential stacking or co-sputtering of precursors as well as using sequential or co-evaporation of elemental sources, leading to high-efficient solar cells. In addition, pulsed laser deposition of composite targets and monograin growth by the molten salt method were developed as alternative methods for kesterite layers deposition. This review presents the growing increase of the kesterite-based solar cell efficiencies achieved over the recent years. A historical description of the main issues limiting this efficiency and of the experimental pathways designed to prevent or limit these issues is provided and discussed as well. A final section is dedicated to the description of promising process steps aiming at further improvements of solar cell efficiency, such as alkali doping and bandgap grading. intensive research on Cu 2 ZnSn(S,Se) 4 (CZT(S,Se)) kesterite compounds as CRM-free absorber layers for PV applications is essential. This article aims at establishing a complete overview of the physical routes used for the synthesis of kesterite thin films as absorber layers in solar cells. The following sections are devoted to that objective and will take on the main issues which have been raised so far as well as how the processes have evolved through the years to meet the requirements of the market. Some major advancements in terms of deposition or post-deposition treatments are introduced. Advantages and drawbacks of each of the physical methods presented in this review are described in detail and compared to other physical or chemical synthesis routes. Physical routes: status overviewWe performed an extensive identification of the common processes and methods used for the synthesis of kesterite thin films or for the design of solar cell devices. In order to avoid unnecessary repetitions along this paper, this section first explains these well-known and commonly used experimental processes and methods. Historically, based on the similarities between kesterite and chalcopyrite compounds, the standard device structure adopted for Cu(In,Ga)(S,Se) 2 (CIGSSe) was directly extended to CZTSSe, by simply replacing the CIGSSe absorber layer with a p-type CZTSSe thin film. CZTSSe solar cells are then typically produced using a soda-lime glass (SLG) substrate coated with a sputtered Mo layer acting as rear metallic contact. Typical sputter-deposited Mo layer thickness is around 500 nm up to 1 μm [12]. The kesterite absorber is then deposited onto the Mo layer.The fabrication of this absorber consists in the deposition of a precursor layer via a physical or a chemical route, which is then annealed in a reactive atmosphere containing either S (sulfurization) or Se (selenization). As a common result of the reactive annealing, a thin Mo(S,Se) 2 layer is naturally formed at the CZTSSe/Mo interface, betw...