Selective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates

Wang, Gang; Leys, Maarten; Nguyen, Ngoc Duy; Loo, Roger; Brammertz, Guy; Richard, Olivier; Bender, Hugo; Dekoster, J; Meuris, Marc; Heyns, Marc; Caymax, Matty

doi:10.1149/1.3489355

Cited by 34 publications

(81 citation statements)

References 26 publications

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“…The narrow trenches were made in SiO 2 with fairly standard shallow trench isolation (STI) patterning technologies [40]. After growth, a chemo-mechanical polishing step was performed to remove the overgrown InP material.…”

Section: Methodsmentioning

confidence: 99%

Epitaxial Defects in Nanoscale InP Fin Structures Revealed by Wet-Chemical Etching

et al. 2017

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In this work, we report on wet-chemical defect revealing in InP fin structures relevant for device manufacturing. Both HCl and HBr solutions were explored using bulk InP as a reference. A distinct difference in pit morphology was observed between the two acids, attributed to an anisotropy in step edge reactivity. The morphology of the etch pits in bulk InP suggests that the dislocations are oriented mainly perpendicular to the surface. By studying the influence of the acid concentration on the InP fin recess in nanoscale trenches, it was found that aqueous HCl solution was most suitable for revealing defects. Planar defects in InP fin structures grown by the aspect ratio trapping technique could be visualized as characteristic shallow grooves approximately one nanometer deep. It is challenging to reveal defects in wide-field InP fins. In these structures, dislocations also reach the surface next to stack faults or twinning planes. Due to the inclined nature, dislocation-related pits are only a few atomic layers deep. Extending the pits is limited by the high reactivity of the fin sides and the strong surface roughening during etching. The process window for revealing wet-chemical defects in InP fins is limited.

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Section: Methodsmentioning

confidence: 99%

Epitaxial Defects in Nanoscale InP Fin Structures Revealed by Wet-Chemical Etching

et al. 2017

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“…The InP layer was grown to a height of about 300 nm above the level of the STI. More details of the InP growth conditions are described elsewhere [6][7][8]. Typical results of the InP growth are shown in Fig.…”

Section: Inp Epitaxymentioning

confidence: 99%

Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

Waldron¹,

Wang²,

Nguyen

et al. 2012

ECS Trans.

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We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10 -7 Ω.cm 2 . Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This development is a significant step towards the integration of InGaAs based devices on a standard CMOS platform.

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“…Off-axis substrates are well known for enabling APB-free III-V growth on Si surfaces, as they provide a high density of atomic steps that form double steps at elevated temperatures which are needed to obtain APB-free epitaxial III-V layers (9,10). However, their use for CMOS device fabrication is hampered by issues like the dependency of crystal quality and surface morphology on STI trench orientation (3,12). In addition, off-axis wafers are not standard in Si CMOS industry.…”

Section: Introductionmentioning

confidence: 99%

“…To solve the APB issue, atomic steps have been engineered on unpatterned Si (001) substrates in the case of GaP growth (10,11). In contrast to a Si surface, the double steps on a Ge surface can be formed at a lower temperature (3,14). Moreover, the lattice mismatch between InP and Ge is only half of that between InP and Si, which renders the easier nucleation of InP on Ge.…”

Section: Introductionmentioning

confidence: 99%

(Invited) Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

Loo¹,

Wang

Orzali³

et al. 2011

ECS Trans.

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We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

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Selective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates

Cited by 34 publications

References 26 publications

Epitaxial Defects in Nanoscale InP Fin Structures Revealed by Wet-Chemical Etching

Epitaxial Defects in Nanoscale InP Fin Structures Revealed by Wet-Chemical Etching

Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

(Invited) Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

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