We have made AlGaN∕GaN high electron mobility transistors with a Si3N4 passivation layer that was deposited in situ in our metal-organic chemical-vapor deposition reactor in the same growth sequence as the rest of the layer stack. The Si3N4 is shown to be of high quality and stoichiometric in composition. It reduces the relaxation, cracking, and surface roughness of the AlGaN layer. It also neutralizes the charges at the top AlGaN interface, which leads to a higher two-dimensional electron-gas density. Moreover, it protects the surface during processing and improves the Ohmic source and drain contacts. This leads to devices with greatly improved characteristics.

In this work, we report on the growth by metalorganic vapor phase epitaxy (MOVPE) of GaN layers on AlN/Si(111) templates with step-graded AlGaN intermediate layers. First, we will discuss the optimization of the AlN/Si(111) templates and then we will discuss the incorporation of step-graded AlGaN intermediate layers. It is found that the growth stress in GaN on high-temperature (HT) AlN/Si(111) templates is compressive, although, due to relaxation, the stress we have measured is much lower than the theoretical value. In order to prevent the stress relaxation, step-graded AlGaN layers are introduced and a crack-free GaN epitaxial layer of thickness .1 mm is demonstrated. Under optimized growth conditions, the total layer stack, exceeding 2 mm in total, is kept under compressive stress, and the radius of the convex wafer bowing is as large as 119 m. The crystalline quality of the GaN layers is examined by highresolution x-ray diffraction (HR-XRD), and the full-width-at-half maximums (FWHMs) of the x-ray rocking curve (0002) v-scan and (ÿ1015) v-scan are 790 arc sec and 730 arc sec, respectively. It is found by cross-sectional transmission electron microscopy (TEM) that the step-graded AlGaN layers terminate or bend the dislocations at the interfaces.

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation ͑STI͒ structures on Si͑001͒ substrates 6°off-cut toward ͑111͒. Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO 2 . However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in ͓110͔ trenches. High quality InP layers were obtained in the top of the trenches along ͓110͔. The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2.

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In this work, we demonstrate the selective area growth of high quality InP layers in submicron trenches on exactly (001) oriented Si substrates by using a thin Ge buffer layer. Antiphase domain boundaries were avoided by annealing at the Ge surface roughening temperature to create additional atomic steps on the Ge buffer layer. The mechanism of Ge surface atomic step formation and the corresponding step density control method are illustrated. The elimination of antiphase boundaries from the optimized Ge buffer layer, together with the defect necking effect, yield defect-free top InP layers inside the trenches.